jishu.vhd

来自「简单的数字频率计」· VHDL 代码 · 共 34 行

library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity jishu is
  port (cp:in std_logic;
		rd:in std_logic;
		c:out std_logic;
		qa,qb,qc,qd:out unsigned(3 downto 0));
end jishu;

architecture jishu_arch of jishu is
signal iqa,iqb,iqc,iqd:unsigned(3 downto 0);
signal tc:std_logic;
begin
process(cp,rd,iqa,iqb,iqc,iqd)
begin 
  if rd='0' 
  then iqa<="0000";iqb<="0000";iqc<="0000";iqd<="0000";tc<='0';
  elsif (cp'event)and(cp='1') then
  if iqd<9 then iqd<=iqd+1; else iqd<="0000";
   if iqc<9 then iqc<=iqc+1; else iqc<="0000";
    if iqb<9 then iqb<=iqb+1; else iqb<="0000";
     if iqa<9 then iqa<=iqa+1; else tc<='1';
  end if;end if;end if;end if;
  end if;
end process;
process(rd)
begin
if (rd='0')and(rd'event) then qa<=iqa;qb<=iqb;qc<=iqc;qd<=iqd;c<=tc;
end if;
end process;
end jishu_arch;