xx.vhd

来自「简单的数字频率计」· VHDL 代码 · 共 21 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity xx is
  port(c:in std_logic;
		r:in std_logic;
		q:out std_logic);
end xx;

architecture x of xx is
variable y:std_logic;
begin
  process(c,y)
	begin
	y<='1';
 	q<=y;
	y<='0';
  end process;
end x;