xianshi.vhd

简单的数字频率计

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity xianshi is
port(a,b,c:in unsigned(3 downto 0);
	 clk:in std_logic;
	 dw:in std_logic;
	 aa,bb,cc,dd,ee,ff,gg,hh:out std_logic;
	 sel:out unsigned(2 downto 0));
end xianshi;

architecture xianshi_arch of xianshi is
signal isel:unsigned(2 downto 0);
signal tp:unsigned(3 downto 0);
begin
scan:process(clk)
	begin
	if (clk'event)and(clk='1')then
	if isel=4 then isel<="010";
	elsif isel=2 then isel<="001";
	else isel<="100";
	end if;
	sel<=isel;
	end if;
 end process;

xianshi:process(dw)
  begin
	
	if isel=4 then tp<=c;
	elsif isel=2 then tp<=a;
	else tp<=b;
	end if;

	case tp is
	when "0000" => aa<='1';bb<='1';cc<='1';dd<='1';ee<='1';ff<='1';gg<='0';
	when "0001" => aa<='0';bb<='1';cc<='1';dd<='0';ee<='0';ff<='0';gg<='0';
	when "0010" => aa<='1';bb<='1';cc<='0';dd<='1';ee<='1';ff<='0';gg<='1';
	when "0011" => aa<='1';bb<='1';cc<='1';dd<='1';ee<='0';ff<='0';gg<='1';
	when "0100" => aa<='0';bb<='1';cc<='1';dd<='0';ee<='0';ff<='1';gg<='1';
	when "0101" => aa<='1';bb<='0';cc<='1';dd<='1';ee<='0';ff<='1';gg<='1';
	when "0110" => aa<='0';bb<='0';cc<='1';dd<='1';ee<='1';ff<='1';gg<='1';
	when "0111" => aa<='1';bb<='1';cc<='1';dd<='0';ee<='0';ff<='0';gg<='0';
	when "1000" => aa<='1';bb<='1';cc<='1';dd<='1';ee<='1';ff<='1';gg<='1';
    when "1001" => aa<='1';bb<='1';cc<='1';dd<='0';ee<='0';ff<='1';gg<='1';
    when others => aa<='0';bb<='0';cc<='0';dd<='0';ee<='0';ff<='0';gg<='1';
    end case;
    hh<=isel(1)and dw;
end process;
end xianshi_arch;