jk_ff.tan.summary

用VERILOG语言实现了J-K触发器,可综合可仿真通过

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.300 ns
From           : J
To             : Q~reg0
From Clock     : 
To Clock       : C
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 2.800 ns
From           : QN~reg0
To             : QN
From Clock     : C
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.800 ns
From           : J
To             : Q~reg0
From Clock     : 
To Clock       : C
Failed Paths   : 0

Type           : Clock Setup: 'C'
Slack          : N/A
Required Time  : None
Actual Time    : 175.44 MHz ( period = 5.700 ns )
From           : Q~reg0
To             : QN~reg0
From Clock     : C
To Clock       : C
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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