jk_ff.tan.rpt

用VERILOG语言实现了J-K触发器,可综合可仿真通过

+---------------------------------------------------------------+
; tsu                                                           ;
+-------+--------------+------------+------+---------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To      ; To Clock ;
+-------+--------------+------------+------+---------+----------+
; N/A   ; None         ; 3.300 ns   ; K    ; QN~reg0 ; C        ;
; N/A   ; None         ; 3.300 ns   ; K    ; Q~reg0  ; C        ;
; N/A   ; None         ; 3.300 ns   ; J    ; QN~reg0 ; C        ;
; N/A   ; None         ; 3.300 ns   ; J    ; Q~reg0  ; C        ;
+-------+--------------+------------+------+---------+----------+


+---------------------------------------------------------------+
; tco                                                           ;
+-------+--------------+------------+---------+----+------------+
; Slack ; Required tco ; Actual tco ; From    ; To ; From Clock ;
+-------+--------------+------------+---------+----+------------+
; N/A   ; None         ; 2.800 ns   ; Q~reg0  ; Q  ; C          ;
; N/A   ; None         ; 2.800 ns   ; QN~reg0 ; QN ; C          ;
+-------+--------------+------------+---------+----+------------+


+---------------------------------------------------------------------+
; th                                                                  ;
+---------------+-------------+-----------+------+---------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To      ; To Clock ;
+---------------+-------------+-----------+------+---------+----------+
; N/A           ; None        ; -0.800 ns ; K    ; QN~reg0 ; C        ;
; N/A           ; None        ; -0.800 ns ; K    ; Q~reg0  ; C        ;
; N/A           ; None        ; -0.800 ns ; J    ; QN~reg0 ; C        ;
; N/A           ; None        ; -0.800 ns ; J    ; Q~reg0  ; C        ;
+---------------+-------------+-----------+------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Tue Aug 08 20:39:13 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off JK_FF -c JK_FF
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "C" is an undefined clock
Info: Clock "C" has Internal fmax of 175.44 MHz between source register "QN~reg0" and destination register "Q~reg0" (period= 5.7 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 3; REG Node = 'QN~reg0'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC2; Fanout = 3; REG Node = 'Q~reg0'
        Info: Total cell delay = 2.600 ns ( 72.22 % )
        Info: Total interconnect delay = 1.000 ns ( 27.78 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "C" to destination register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'C'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC2; Fanout = 3; REG Node = 'Q~reg0'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
        Info: - Longest clock path from clock "C" to source register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'C'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 3; REG Node = 'QN~reg0'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: tsu for register "QN~reg0" (data pin = "K", clock pin = "C") is 3.300 ns
    Info: + Longest pin to register delay is 3.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_21; Fanout = 4; PIN Node = 'K'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC1; Fanout = 3; REG Node = 'QN~reg0'
        Info: Total cell delay = 2.800 ns ( 73.68 % )
        Info: Total interconnect delay = 1.000 ns ( 26.32 % )
    Info: + Micro setup delay of destination is 0.800 ns
    Info: - Shortest clock path from clock "C" to destination register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'C'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 3; REG Node = 'QN~reg0'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: tco from clock "C" to destination pin "Q" through register "Q~reg0" is 2.800 ns
    Info: + Longest clock path from clock "C" to source register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'C'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC2; Fanout = 3; REG Node = 'Q~reg0'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Longest register to pin delay is 0.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 3; REG Node = 'Q~reg0'
        Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'Q'
        Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: th for register "QN~reg0" (data pin = "K", clock pin = "C") is -0.800 ns
    Info: + Longest clock path from clock "C" to destination register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'C'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 3; REG Node = 'QN~reg0'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.700 ns
    Info: - Shortest pin to register delay is 3.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_21; Fanout = 4; PIN Node = 'K'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC1; Fanout = 3; REG Node = 'QN~reg0'
        Info: Total cell delay = 2.800 ns ( 73.68 % )
        Info: Total interconnect delay = 1.000 ns ( 26.32 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Aug 08 20:39:13 2006
    Info: Elapsed time: 00:00:01