jk_ff.fit.summary

用VERILOG语言实现了J-K触发器,可综合可仿真通过

Flow Status : Successful - Tue Aug 08 20:39:09 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : JK_FF
Top-level Entity Name : JK_FF
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 2 / 32 ( 6 % )
Total pins : 9 / 36 ( 25 % )
Device : EPM7032SLC44-5
Timing Models : Final