full_adder.fit.summary

来自「用VERILOG语言实现了全加器,可综合可仿真通过」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Tue Aug 08 14:19:59 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : Full_Adder
Top-level Entity Name : Full_Adder
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 2 / 32 ( 6 % )
Total pins : 9 / 36 ( 25 % )
Device : EPM7032SLC44-5
Timing Models : Final