full_adder.map.eqn

用VERILOG语言实现了全加器,可综合可仿真通过

--A1L4 is S~2
A1L4_p2_out = X & !Y;
A1L4_p3_out = !X & Y;
A1L4_or_out = A1L4_p2_out # A1L4_p3_out;
A1L4 = CIN $ A1L4_or_out;


--A1L7 is add~48
A1L7_p1_out = X & Y;
A1L7_p2_out = X & CIN;
A1L7_p3_out = Y & CIN;
A1L7_or_out = A1L7_p1_out # A1L7_p2_out # A1L7_p3_out;
A1L7 = A1L7_or_out;


--X is X
--operation mode is input

X = INPUT();


--Y is Y
--operation mode is input

Y = INPUT();


--CIN is CIN
--operation mode is input

CIN = INPUT();


--S is S
--operation mode is output

S = OUTPUT(A1L4);


--COUT is COUT
--operation mode is output

COUT = OUTPUT(A1L7);