full_adder.fit.eqn

来自「用VERILOG语言实现了全加器,可综合可仿真通过」· EQN 代码 · 共 50 行

--A1L4 is S~2 at LC1
A1L4_p2_out = X & !Y;
A1L4_p3_out = !X & Y;
A1L4_or_out = A1L4_p2_out # A1L4_p3_out;
A1L4 = CIN $ A1L4_or_out;


--A1L11 is add~48 at LC2
A1L11_p1_out = X & Y;
A1L11_p2_out = X & CIN;
A1L11_p3_out = Y & CIN;
A1L11_or_out = A1L11_p1_out # A1L11_p2_out # A1L11_p3_out;
A1L11 = A1L11_or_out;


--X is X at PIN_24
--operation mode is input

X = INPUT();


--Y is Y at PIN_21
--operation mode is input

Y = INPUT();


--CIN is CIN at PIN_25
--operation mode is input

CIN = INPUT();


--S is S at PIN_4
--operation mode is output

S = OUTPUT(A1L4);


--COUT is COUT at PIN_5
--operation mode is output

COUT = OUTPUT(A1L11);