coder_8_3.v

用verilog HDL实现了83编码器.

module Coder_8_3(EN,I0,I1,I2,I3,I4,I5,I6,I7,A2,A1,A0,GS,EO);
input   EN;
input   I0,I1,I2,I3,I4,I5,I6,I7;
output  A2,A1,A0,GS,EO;

reg  A2,A1,A0,GS,EO;

always  @(EN or I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7)
begin
  if(EN ==1'b1)
    {A2,A1,A0,GS,EO}  <=  5'b11111;
  else
    begin
      if(I7 == 1'b0)
        {A2,A1,A0,GS,EO}  <=  5'b00001;
      else if({I7,I6} == 2'b10)
        {A2,A1,A0,GS,EO}  <=  5'b00101;
      else if({I7,I6,I5} == 3'b110)
        {A2,A1,A0,GS,EO}  <=  5'b01001;
      else if({I7,I6,I5,I4} == 4'b1110)
        {A2,A1,A0,GS,EO}  <=  5'b01101;
      else if({I7,I6,I5,I4,I3} == 5'b11110)
        {A2,A1,A0,GS,EO}  <=  5'b10001;
      else if({I7,I6,I5,I4,I3,I2} == 6'b111110)
        {A2,A1,A0,GS,EO}  <=  5'b10101;
      else if({I7,I6,I5,I4,I3,I2,I1} == 7'b1111110)
        {A2,A1,A0,GS,EO}  <=  5'b11001;
      else if({I7,I6,I5,I4,I3,I2,I1,I0} == 8'b11111110)
        {A2,A1,A0,GS,EO}  <=  5'b11101;
      else if({I7,I6,I5,I4,I3,I2,I1,I0} == 8'b11111111)
        {A2,A1,A0,GS,EO}  <=  5'b11110;
      else
        {A2,A1,A0,GS,EO}  <=  5'b11111;
    end
end

endmodule