uart.tan.summary

用ＦＰＧＡ

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.829 ns
From           : txdbuf_in[0]
To             : transfer:inst2|txds
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.935 ns
From           : reciever:inst1|rbuf[0]
To             : rec_buf[0]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.039 ns
From           : reset
To             : transfer:inst2|xcnt16[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 203.42 MHz ( period = 4.916 ns )
From           : baud:inst|cnt[0]
To             : baud:inst|cnt[30]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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