📄 uart.map.rpt
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+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------+--------------+
; |Uart ; 226 (0) ; 134 (0) ; 0 ; 0 ; 0 ; 0 ; 23 ; 0 ; |Uart ; work ;
; |baud:inst| ; 74 (74) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Uart|baud:inst ; work ;
; |reciever:inst1| ; 79 (79) ; 58 (58) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Uart|reciever:inst1 ; work ;
; |transfer:inst2| ; 73 (73) ; 43 (43) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Uart|transfer:inst2 ; work ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
Encoding Type: One-Hot
+--------------------------------------------------------------------------------------------+
; State Machine - |Uart|transfer:inst2|state ;
+---------------+--------------+---------------+--------------+---------------+--------------+
; Name ; state.x_stop ; state.x_shift ; state.x_wait ; state.x_start ; state.x_idle ;
+---------------+--------------+---------------+--------------+---------------+--------------+
; state.x_idle ; 0 ; 0 ; 0 ; 0 ; 0 ;
; state.x_start ; 0 ; 0 ; 0 ; 1 ; 1 ;
; state.x_wait ; 0 ; 0 ; 1 ; 0 ; 1 ;
; state.x_shift ; 0 ; 1 ; 0 ; 0 ; 1 ;
; state.x_stop ; 1 ; 0 ; 0 ; 0 ; 1 ;
+---------------+--------------+---------------+--------------+---------------+--------------+
Encoding Type: One-Hot
+------------------------------------------------------------------------------------------------+
; State Machine - |Uart|reciever:inst1|state ;
+----------------+--------------+----------------+--------------+----------------+---------------+
; Name ; state.r_stop ; state.r_sample ; state.r_wait ; state.r_center ; state.r_start ;
+----------------+--------------+----------------+--------------+----------------+---------------+
; state.r_start ; 0 ; 0 ; 0 ; 0 ; 0 ;
; state.r_center ; 0 ; 0 ; 0 ; 1 ; 1 ;
; state.r_wait ; 0 ; 0 ; 1 ; 0 ; 1 ;
; state.r_sample ; 0 ; 1 ; 0 ; 0 ; 1 ;
; state.r_stop ; 1 ; 0 ; 0 ; 0 ; 1 ;
+----------------+--------------+----------------+--------------+----------------+---------------+
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; transfer:inst2|xcnt16[4] ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 1 ; ;
+---------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 134 ;
; Number of registers using Synchronous Clear ; 64 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 49 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 81 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; transfer:inst2|txds ; 2 ;
; Total number of inverted registers = 1 ; ;
+----------------------------------------+---------+
+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
; 4:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |Uart|reciever:inst1|\pro2:rcnt[21] ;
; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |Uart|transfer:inst2|xbitcnt[19] ;
; 6:1 ; 4 bits ; 16 LEs ; 4 LEs ; 12 LEs ; Yes ; |Uart|reciever:inst1|\pro2:count[0] ;
; 8:1 ; 5 bits ; 25 LEs ; 5 LEs ; 20 LEs ; Yes ; |Uart|transfer:inst2|xcnt16[4] ;
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |Uart|reciever:inst1|state~6 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
+-------------------------------------------------------------+
; Parameter Settings for User Entity Instance: reciever:inst1 ;
+----------------+-------+------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------+
; framlenr ; 8 ; Untyped ;
+----------------+-------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------+
; Parameter Settings for User Entity Instance: transfer:inst2 ;
+----------------+-------+------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------+
; framlent ; 8 ; Untyped ;
+----------------+-------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Thu Feb 28 15:59:16 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Uart -c Uart
Info: Found 2 design units, including 1 entities, in source file baud.vhd
Info: Found design unit 1: baud-behave
Info: Found entity 1: baud
Info: Found 2 design units, including 1 entities, in source file transfer.vhd
Info: Found design unit 1: transfer-behave
Info: Found entity 1: transfer
Info: Found 2 design units, including 1 entities, in source file reciever.vhd
Info: Found design unit 1: reciever-behave
Info: Found entity 1: reciever
Info: Found 1 design units, including 1 entities, in source file Uart.bdf
Info: Found entity 1: Uart
Info: Elaborating entity "Uart" for the top level hierarchy
Info: Elaborating entity "reciever" for hierarchy "reciever:inst1"
Info: Elaborating entity "baud" for hierarchy "baud:inst"
Info: Elaborating entity "transfer" for hierarchy "transfer:inst2"
Info: State machine "|Uart|transfer:inst2|state" contains 5 states
Info: State machine "|Uart|reciever:inst1|state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|Uart|transfer:inst2|state"
Info: Encoding result for state machine "|Uart|transfer:inst2|state"
Info: Completed encoding using 5 state bits
Info: Encoded state bit "transfer:inst2|state.x_stop"
Info: Encoded state bit "transfer:inst2|state.x_shift"
Info: Encoded state bit "transfer:inst2|state.x_wait"
Info: Encoded state bit "transfer:inst2|state.x_start"
Info: Encoded state bit "transfer:inst2|state.x_idle"
Info: State "|Uart|transfer:inst2|state.x_idle" uses code string "00000"
Info: State "|Uart|transfer:inst2|state.x_start" uses code string "00011"
Info: State "|Uart|transfer:inst2|state.x_wait" uses code string "00101"
Info: State "|Uart|transfer:inst2|state.x_shift" uses code string "01001"
Info: State "|Uart|transfer:inst2|state.x_stop" uses code string "10001"
Info: Selected Auto state machine encoding method for state machine "|Uart|reciever:inst1|state"
Info: Encoding result for state machine "|Uart|reciever:inst1|state"
Info: Completed encoding using 5 state bits
Info: Encoded state bit "reciever:inst1|state.r_stop"
Info: Encoded state bit "reciever:inst1|state.r_sample"
Info: Encoded state bit "reciever:inst1|state.r_wait"
Info: Encoded state bit "reciever:inst1|state.r_center"
Info: Encoded state bit "reciever:inst1|state.r_start"
Info: State "|Uart|reciever:inst1|state.r_start" uses code string "00000"
Info: State "|Uart|reciever:inst1|state.r_center" uses code string "00011"
Info: State "|Uart|reciever:inst1|state.r_wait" uses code string "00101"
Info: State "|Uart|reciever:inst1|state.r_sample" uses code string "01001"
Info: State "|Uart|reciever:inst1|state.r_stop" uses code string "10001"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (14130): Reduced register "transfer:inst2|xcnt16[4]" with stuck data_in port to stuck value GND
Critical Warning: Ignored Power-Up Level option on the following registers
Critical Warning: Register baud:inst|cnt[31] will power up to Low
Critical Warning: Register baud:inst|cnt[0] will power up to Low
Info: Implemented 257 device resources after synthesis - the final resource count might be different
Info: Implemented 12 input pins
Info: Implemented 11 output pins
Info: Implemented 234 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
Info: Allocated 163 megabytes of memory during processing
Info: Processing ended: Thu Feb 28 15:59:23 2008
Info: Elapsed time: 00:00:07
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