uart.tan.qmsg

用ＦＰＧＡ

{ "Info" "ITDB_TH_RESULT" "transfer:inst2\|xcnt16\[0\] reset clk 3.039 ns register " "Info: th for register \"transfer:inst2\|xcnt16\[0\]\" (data pin = \"reset\", clock pin = \"clk\") is 3.039 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.622 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.622 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Uart.bdf" "" { Schematic "E:/My_Design/VHDL/Uart/Uart.bdf" { { 16 -136 32 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.913 ns) + CELL(0.787 ns) 3.699 ns baud:inst\|bclk 2 REG LCFF_X34_Y9_N21 1 " "Info: 2: + IC(1.913 ns) + CELL(0.787 ns) = 3.699 ns; Loc. = LCFF_X34_Y9_N21; Fanout = 1; REG Node = 'baud:inst\|bclk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { clk baud:inst|bclk } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.382 ns) + CELL(0.000 ns) 5.081 ns baud:inst\|bclk~clkctrl 3 COMB CLKCTRL_G12 101 " "Info: 3: + IC(1.382 ns) + CELL(0.000 ns) = 5.081 ns; Loc. = CLKCTRL_G12; Fanout = 101; COMB Node = 'baud:inst\|bclk~clkctrl'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.382 ns" { baud:inst|bclk baud:inst|bclk~clkctrl } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.004 ns) + CELL(0.537 ns) 6.622 ns transfer:inst2\|xcnt16\[0\] 4 REG LCFF_X45_Y28_N15 5 " "Info: 4: + IC(1.004 ns) + CELL(0.537 ns) = 6.622 ns; Loc. = LCFF_X45_Y28_N15; Fanout = 5; REG Node = 'transfer:inst2\|xcnt16\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.541 ns" { baud:inst|bclk~clkctrl transfer:inst2|xcnt16[0] } "NODE_NAME" } } { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 35.08 % ) " "Info: Total cell delay = 2.323 ns ( 35.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.299 ns ( 64.92 % ) " "Info: Total interconnect delay = 4.299 ns ( 64.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.622 ns" { clk baud:inst|bclk baud:inst|bclk~clkctrl transfer:inst2|xcnt16[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.622 ns" { clk {} clk~combout {} baud:inst|bclk {} baud:inst|bclk~clkctrl {} transfer:inst2|xcnt16[0] {} } { 0.000ns 0.000ns 1.913ns 1.382ns 1.004ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.849 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns reset 1 PIN PIN_P1 10 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 10; PIN Node = 'reset'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "Uart.bdf" "" { Schematic "E:/My_Design/VHDL/Uart/Uart.bdf" { { 32 -136 32 48 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.190 ns) + CELL(0.660 ns) 3.849 ns transfer:inst2\|xcnt16\[0\] 2 REG LCFF_X45_Y28_N15 5 " "Info: 2: + IC(2.190 ns) + CELL(0.660 ns) = 3.849 ns; Loc. = LCFF_X45_Y28_N15; Fanout = 5; REG Node = 'transfer:inst2\|xcnt16\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.850 ns" { reset transfer:inst2|xcnt16[0] } "NODE_NAME" } } { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.659 ns ( 43.10 % ) " "Info: Total cell delay = 1.659 ns ( 43.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.190 ns ( 56.90 % ) " "Info: Total interconnect delay = 2.190 ns ( 56.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.849 ns" { reset transfer:inst2|xcnt16[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.849 ns" { reset {} reset~combout {} transfer:inst2|xcnt16[0] {} } { 0.000ns 0.000ns 2.190ns } { 0.000ns 0.999ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.622 ns" { clk baud:inst|bclk baud:inst|bclk~clkctrl transfer:inst2|xcnt16[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.622 ns" { clk {} clk~combout {} baud:inst|bclk {} baud:inst|bclk~clkctrl {} transfer:inst2|xcnt16[0] {} } { 0.000ns 0.000ns 1.913ns 1.382ns 1.004ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.849 ns" { reset transfer:inst2|xcnt16[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.849 ns" { reset {} reset~combout {} transfer:inst2|xcnt16[0] {} } { 0.000ns 0.000ns 2.190ns } { 0.000ns 0.999ns 0.660ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "119 " "Info: Allocated 119 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 28 16:00:09 2008 " "Info: Processing ended: Thu Feb 28 16:00:09 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2