uart.tan.qmsg

用ＦＰＧＡ

{ "Info" "ITDB_TSU_RESULT" "transfer:inst2\|txds txdbuf_in\[0\] clk 1.829 ns register " "Info: tsu for register \"transfer:inst2\|txds\" (data pin = \"txdbuf_in\[0\]\", clock pin = \"clk\") is 1.829 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.487 ns + Longest pin register " "Info: + Longest pin to register delay is 8.487 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.830 ns) 0.830 ns txdbuf_in\[0\] 1 PIN PIN_F15 1 " "Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_F15; Fanout = 1; PIN Node = 'txdbuf_in\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { txdbuf_in[0] } "NODE_NAME" } } { "Uart.bdf" "" { Schematic "E:/My_Design/VHDL/Uart/Uart.bdf" { { 200 -144 24 216 "txdbuf_in\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.189 ns) + CELL(0.438 ns) 6.457 ns transfer:inst2\|Mux0~33 2 COMB LCCOMB_X45_Y28_N24 1 " "Info: 2: + IC(5.189 ns) + CELL(0.438 ns) = 6.457 ns; Loc. = LCCOMB_X45_Y28_N24; Fanout = 1; COMB Node = 'transfer:inst2\|Mux0~33'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.627 ns" { txdbuf_in[0] transfer:inst2|Mux0~33 } "NODE_NAME" } } { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.275 ns) 6.986 ns transfer:inst2\|Mux0~34 3 COMB LCCOMB_X45_Y28_N16 1 " "Info: 3: + IC(0.254 ns) + CELL(0.275 ns) = 6.986 ns; Loc. = LCCOMB_X45_Y28_N16; Fanout = 1; COMB Node = 'transfer:inst2\|Mux0~34'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.529 ns" { transfer:inst2|Mux0~33 transfer:inst2|Mux0~34 } "NODE_NAME" } } { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.270 ns) + CELL(0.436 ns) 7.692 ns transfer:inst2\|Selector10~297 4 COMB LCCOMB_X45_Y28_N8 1 " "Info: 4: + IC(0.270 ns) + CELL(0.436 ns) = 7.692 ns; Loc. = LCCOMB_X45_Y28_N8; Fanout = 1; COMB Node = 'transfer:inst2\|Selector10~297'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.706 ns" { transfer:inst2|Mux0~34 transfer:inst2|Selector10~297 } "NODE_NAME" } } { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.275 ns) 8.403 ns transfer:inst2\|Selector10~298 5 COMB LCCOMB_X44_Y28_N10 1 " "Info: 5: + IC(0.436 ns) + CELL(0.275 ns) = 8.403 ns; Loc. = LCCOMB_X44_Y28_N10; Fanout = 1; COMB Node = 'transfer:inst2\|Selector10~298'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.711 ns" { transfer:inst2|Selector10~297 transfer:inst2|Selector10~298 } "NODE_NAME" } } { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 8.487 ns transfer:inst2\|txds 6 REG LCFF_X44_Y28_N11 2 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 8.487 ns; Loc. = LCFF_X44_Y28_N11; Fanout = 2; REG Node = 'transfer:inst2\|txds'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { transfer:inst2|Selector10~298 transfer:inst2|txds } "NODE_NAME" } } { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.338 ns ( 27.55 % ) " "Info: Total cell delay = 2.338 ns ( 27.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.149 ns ( 72.45 % ) " "Info: Total interconnect delay = 6.149 ns ( 72.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.487 ns" { txdbuf_in[0] transfer:inst2|Mux0~33 transfer:inst2|Mux0~34 transfer:inst2|Selector10~297 transfer:inst2|Selector10~298 transfer:inst2|txds } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.487 ns" { txdbuf_in[0] {} txdbuf_in[0]~combout {} transfer:inst2|Mux0~33 {} transfer:inst2|Mux0~34 {} transfer:inst2|Selector10~297 {} transfer:inst2|Selector10~298 {} transfer:inst2|txds {} } { 0.000ns 0.000ns 5.189ns 0.254ns 0.270ns 0.436ns 0.000ns } { 0.000ns 0.830ns 0.438ns 0.275ns 0.436ns 0.275ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.622 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 6.622 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Uart.bdf" "" { Schematic "E:/My_Design/VHDL/Uart/Uart.bdf" { { 16 -136 32 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.913 ns) + CELL(0.787 ns) 3.699 ns baud:inst\|bclk 2 REG LCFF_X34_Y9_N21 1 " "Info: 2: + IC(1.913 ns) + CELL(0.787 ns) = 3.699 ns; Loc. = LCFF_X34_Y9_N21; Fanout = 1; REG Node = 'baud:inst\|bclk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { clk baud:inst|bclk } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.382 ns) + CELL(0.000 ns) 5.081 ns baud:inst\|bclk~clkctrl 3 COMB CLKCTRL_G12 101 " "Info: 3: + IC(1.382 ns) + CELL(0.000 ns) = 5.081 ns; Loc. = CLKCTRL_G12; Fanout = 101; COMB Node = 'baud:inst\|bclk~clkctrl'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.382 ns" { baud:inst|bclk baud:inst|bclk~clkctrl } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.004 ns) + CELL(0.537 ns) 6.622 ns transfer:inst2\|txds 4 REG LCFF_X44_Y28_N11 2 " "Info: 4: + IC(1.004 ns) + CELL(0.537 ns) = 6.622 ns; Loc. = LCFF_X44_Y28_N11; Fanout = 2; REG Node = 'transfer:inst2\|txds'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.541 ns" { baud:inst|bclk~clkctrl transfer:inst2|txds } "NODE_NAME" } } { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 35.08 % ) " "Info: Total cell delay = 2.323 ns ( 35.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.299 ns ( 64.92 % ) " "Info: Total interconnect delay = 4.299 ns ( 64.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.622 ns" { clk baud:inst|bclk baud:inst|bclk~clkctrl transfer:inst2|txds } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.622 ns" { clk {} clk~combout {} baud:inst|bclk {} baud:inst|bclk~clkctrl {} transfer:inst2|txds {} } { 0.000ns 0.000ns 1.913ns 1.382ns 1.004ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.487 ns" { txdbuf_in[0] transfer:inst2|Mux0~33 transfer:inst2|Mux0~34 transfer:inst2|Selector10~297 transfer:inst2|Selector10~298 transfer:inst2|txds } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.487 ns" { txdbuf_in[0] {} txdbuf_in[0]~combout {} transfer:inst2|Mux0~33 {} transfer:inst2|Mux0~34 {} transfer:inst2|Selector10~297 {} transfer:inst2|Selector10~298 {} transfer:inst2|txds {} } { 0.000ns 0.000ns 5.189ns 0.254ns 0.270ns 0.436ns 0.000ns } { 0.000ns 0.830ns 0.438ns 0.275ns 0.436ns 0.275ns 0.084ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.622 ns" { clk baud:inst|bclk baud:inst|bclk~clkctrl transfer:inst2|txds } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.622 ns" { clk {} clk~combout {} baud:inst|bclk {} baud:inst|bclk~clkctrl {} transfer:inst2|txds {} } { 0.000ns 0.000ns 1.913ns 1.382ns 1.004ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk rec_buf\[0\] reciever:inst1\|rbuf\[0\] 11.935 ns register " "Info: tco from clock \"clk\" to destination pin \"rec_buf\[0\]\" through register \"reciever:inst1\|rbuf\[0\]\" is 11.935 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.617 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.617 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Uart.bdf" "" { Schematic "E:/My_Design/VHDL/Uart/Uart.bdf" { { 16 -136 32 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.913 ns) + CELL(0.787 ns) 3.699 ns baud:inst\|bclk 2 REG LCFF_X34_Y9_N21 1 " "Info: 2: + IC(1.913 ns) + CELL(0.787 ns) = 3.699 ns; Loc. = LCFF_X34_Y9_N21; Fanout = 1; REG Node = 'baud:inst\|bclk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { clk baud:inst|bclk } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.382 ns) + CELL(0.000 ns) 5.081 ns baud:inst\|bclk~clkctrl 3 COMB CLKCTRL_G12 101 " "Info: 3: + IC(1.382 ns) + CELL(0.000 ns) = 5.081 ns; Loc. = CLKCTRL_G12; Fanout = 101; COMB Node = 'baud:inst\|bclk~clkctrl'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.382 ns" { baud:inst|bclk baud:inst|bclk~clkctrl } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.999 ns) + CELL(0.537 ns) 6.617 ns reciever:inst1\|rbuf\[0\] 4 REG LCFF_X46_Y24_N25 1 " "Info: 4: + IC(0.999 ns) + CELL(0.537 ns) = 6.617 ns; Loc. = LCFF_X46_Y24_N25; Fanout = 1; REG Node = 'reciever:inst1\|rbuf\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.536 ns" { baud:inst|bclk~clkctrl reciever:inst1|rbuf[0] } "NODE_NAME" } } { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 35.11 % ) " "Info: Total cell delay = 2.323 ns ( 35.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.294 ns ( 64.89 % ) " "Info: Total interconnect delay = 4.294 ns ( 64.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.617 ns" { clk baud:inst|bclk baud:inst|bclk~clkctrl reciever:inst1|rbuf[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.617 ns" { clk {} clk~combout {} baud:inst|bclk {} baud:inst|bclk~clkctrl {} reciever:inst1|rbuf[0] {} } { 0.000ns 0.000ns 1.913ns 1.382ns 0.999ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.068 ns + Longest register pin " "Info: + Longest register to pin delay is 5.068 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reciever:inst1\|rbuf\[0\] 1 REG LCFF_X46_Y24_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X46_Y24_N25; Fanout = 1; REG Node = 'reciever:inst1\|rbuf\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reciever:inst1|rbuf[0] } "NODE_NAME" } } { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.280 ns) + CELL(2.788 ns) 5.068 ns rec_buf\[0\] 2 PIN PIN_AD17 0 " "Info: 2: + IC(2.280 ns) + CELL(2.788 ns) = 5.068 ns; Loc. = PIN_AD17; Fanout = 0; PIN Node = 'rec_buf\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.068 ns" { reciever:inst1|rbuf[0] rec_buf[0] } "NODE_NAME" } } { "Uart.bdf" "" { Schematic "E:/My_Design/VHDL/Uart/Uart.bdf" { { 368 640 816 384 "rec_buf\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.788 ns ( 55.01 % ) " "Info: Total cell delay = 2.788 ns ( 55.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.280 ns ( 44.99 % ) " "Info: Total interconnect delay = 2.280 ns ( 44.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.068 ns" { reciever:inst1|rbuf[0] rec_buf[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.068 ns" { reciever:inst1|rbuf[0] {} rec_buf[0] {} } { 0.000ns 2.280ns } { 0.000ns 2.788ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.617 ns" { clk baud:inst|bclk baud:inst|bclk~clkctrl reciever:inst1|rbuf[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.617 ns" { clk {} clk~combout {} baud:inst|bclk {} baud:inst|bclk~clkctrl {} reciever:inst1|rbuf[0] {} } { 0.000ns 0.000ns 1.913ns 1.382ns 0.999ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.068 ns" { reciever:inst1|rbuf[0] rec_buf[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.068 ns" { reciever:inst1|rbuf[0] {} rec_buf[0] {} } { 0.000ns 2.280ns } { 0.000ns 2.788ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}