📄 uart.tan.qmsg
字号:
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "baud:inst\|bclk " "Info: Detected ripple clock \"baud:inst\|bclk\" as buffer" { } { { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 10 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "baud:inst\|bclk" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register baud:inst\|cnt\[0\] register baud:inst\|cnt\[30\] 203.42 MHz 4.916 ns Internal " "Info: Clock \"clk\" has Internal fmax of 203.42 MHz between source register \"baud:inst\|cnt\[0\]\" and destination register \"baud:inst\|cnt\[30\]\" (period= 4.916 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.702 ns + Longest register register " "Info: + Longest register to register delay is 4.702 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns baud:inst\|cnt\[0\] 1 REG LCFF_X34_Y9_N19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y9_N19; Fanout = 2; REG Node = 'baud:inst\|cnt\[0\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { baud:inst|cnt[0] } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.503 ns) + CELL(0.393 ns) 0.896 ns baud:inst\|Add0~2057 2 COMB LCCOMB_X35_Y9_N0 2 " "Info: 2: + IC(0.503 ns) + CELL(0.393 ns) = 0.896 ns; Loc. = LCCOMB_X35_Y9_N0; Fanout = 2; COMB Node = 'baud:inst\|Add0~2057'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.896 ns" { baud:inst|cnt[0] baud:inst|Add0~2057 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.967 ns baud:inst\|Add0~2059 3 COMB LCCOMB_X35_Y9_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.967 ns; Loc. = LCCOMB_X35_Y9_N2; Fanout = 2; COMB Node = 'baud:inst\|Add0~2059'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2057 baud:inst|Add0~2059 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.038 ns baud:inst\|Add0~2061 4 COMB LCCOMB_X35_Y9_N4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.038 ns; Loc. = LCCOMB_X35_Y9_N4; Fanout = 2; COMB Node = 'baud:inst\|Add0~2061'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2059 baud:inst|Add0~2061 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.109 ns baud:inst\|Add0~2063 5 COMB LCCOMB_X35_Y9_N6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.109 ns; Loc. = LCCOMB_X35_Y9_N6; Fanout = 2; COMB Node = 'baud:inst\|Add0~2063'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2061 baud:inst|Add0~2063 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.180 ns baud:inst\|Add0~2065 6 COMB LCCOMB_X35_Y9_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.180 ns; Loc. = LCCOMB_X35_Y9_N8; Fanout = 2; COMB Node = 'baud:inst\|Add0~2065'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2063 baud:inst|Add0~2065 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.251 ns baud:inst\|Add0~2067 7 COMB LCCOMB_X35_Y9_N10 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.251 ns; Loc. = LCCOMB_X35_Y9_N10; Fanout = 2; COMB Node = 'baud:inst\|Add0~2067'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2065 baud:inst|Add0~2067 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.322 ns baud:inst\|Add0~2069 8 COMB LCCOMB_X35_Y9_N12 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.322 ns; Loc. = LCCOMB_X35_Y9_N12; Fanout = 2; COMB Node = 'baud:inst\|Add0~2069'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2067 baud:inst|Add0~2069 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 1.481 ns baud:inst\|Add0~2071 9 COMB LCCOMB_X35_Y9_N14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.159 ns) = 1.481 ns; Loc. = LCCOMB_X35_Y9_N14; Fanout = 2; COMB Node = 'baud:inst\|Add0~2071'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { baud:inst|Add0~2069 baud:inst|Add0~2071 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.552 ns baud:inst\|Add0~2073 10 COMB LCCOMB_X35_Y9_N16 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.552 ns; Loc. = LCCOMB_X35_Y9_N16; Fanout = 2; COMB Node = 'baud:inst\|Add0~2073'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2071 baud:inst|Add0~2073 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.623 ns baud:inst\|Add0~2075 11 COMB LCCOMB_X35_Y9_N18 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.623 ns; Loc. = LCCOMB_X35_Y9_N18; Fanout = 2; COMB Node = 'baud:inst\|Add0~2075'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2073 baud:inst|Add0~2075 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.694 ns baud:inst\|Add0~2077 12 COMB LCCOMB_X35_Y9_N20 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.694 ns; Loc. = LCCOMB_X35_Y9_N20; Fanout = 2; COMB Node = 'baud:inst\|Add0~2077'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2075 baud:inst|Add0~2077 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.765 ns baud:inst\|Add0~2079 13 COMB LCCOMB_X35_Y9_N22 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 1.765 ns; Loc. = LCCOMB_X35_Y9_N22; Fanout = 2; COMB Node = 'baud:inst\|Add0~2079'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2077 baud:inst|Add0~2079 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.836 ns baud:inst\|Add0~2081 14 COMB LCCOMB_X35_Y9_N24 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 1.836 ns; Loc. = LCCOMB_X35_Y9_N24; Fanout = 2; COMB Node = 'baud:inst\|Add0~2081'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2079 baud:inst|Add0~2081 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.907 ns baud:inst\|Add0~2083 15 COMB LCCOMB_X35_Y9_N26 2 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 1.907 ns; Loc. = LCCOMB_X35_Y9_N26; Fanout = 2; COMB Node = 'baud:inst\|Add0~2083'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2081 baud:inst|Add0~2083 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.978 ns baud:inst\|Add0~2085 16 COMB LCCOMB_X35_Y9_N28 2 " "Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 1.978 ns; Loc. = LCCOMB_X35_Y9_N28; Fanout = 2; COMB Node = 'baud:inst\|Add0~2085'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2083 baud:inst|Add0~2085 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 2.124 ns baud:inst\|Add0~2087 17 COMB LCCOMB_X35_Y9_N30 2 " "Info: 17: + IC(0.000 ns) + CELL(0.146 ns) = 2.124 ns; Loc. = LCCOMB_X35_Y9_N30; Fanout = 2; COMB Node = 'baud:inst\|Add0~2087'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.146 ns" { baud:inst|Add0~2085 baud:inst|Add0~2087 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.195 ns baud:inst\|Add0~2089 18 COMB LCCOMB_X35_Y8_N0 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 2.195 ns; Loc. = LCCOMB_X35_Y8_N0; Fanout = 2; COMB Node = 'baud:inst\|Add0~2089'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2087 baud:inst|Add0~2089 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.266 ns baud:inst\|Add0~2091 19 COMB LCCOMB_X35_Y8_N2 2 " "Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 2.266 ns; Loc. = LCCOMB_X35_Y8_N2; Fanout = 2; COMB Node = 'baud:inst\|Add0~2091'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2089 baud:inst|Add0~2091 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.337 ns baud:inst\|Add0~2093 20 COMB LCCOMB_X35_Y8_N4 2 " "Info: 20: + IC(0.000 ns) + CELL(0.071 ns) = 2.337 ns; Loc. = LCCOMB_X35_Y8_N4; Fanout = 2; COMB Node = 'baud:inst\|Add0~2093'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2091 baud:inst|Add0~2093 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.408 ns baud:inst\|Add0~2095 21 COMB LCCOMB_X35_Y8_N6 2 " "Info: 21: + IC(0.000 ns) + CELL(0.071 ns) = 2.408 ns; Loc. = LCCOMB_X35_Y8_N6; Fanout = 2; COMB Node = 'baud:inst\|Add0~2095'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2093 baud:inst|Add0~2095 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.479 ns baud:inst\|Add0~2097 22 COMB LCCOMB_X35_Y8_N8 2 " "Info: 22: + IC(0.000 ns) + CELL(0.071 ns) = 2.479 ns; Loc. = LCCOMB_X35_Y8_N8; Fanout = 2; COMB Node = 'baud:inst\|Add0~2097'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2095 baud:inst|Add0~2097 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.550 ns baud:inst\|Add0~2099 23 COMB LCCOMB_X35_Y8_N10 2 " "Info: 23: + IC(0.000 ns) + CELL(0.071 ns) = 2.550 ns; Loc. = LCCOMB_X35_Y8_N10; Fanout = 2; COMB Node = 'baud:inst\|Add0~2099'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2097 baud:inst|Add0~2099 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.621 ns baud:inst\|Add0~2101 24 COMB LCCOMB_X35_Y8_N12 2 " "Info: 24: + IC(0.000 ns) + CELL(0.071 ns) = 2.621 ns; Loc. = LCCOMB_X35_Y8_N12; Fanout = 2; COMB Node = 'baud:inst\|Add0~2101'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2099 baud:inst|Add0~2101 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 2.780 ns baud:inst\|Add0~2103 25 COMB LCCOMB_X35_Y8_N14 2 " "Info: 25: + IC(0.000 ns) + CELL(0.159 ns) = 2.780 ns; Loc. = LCCOMB_X35_Y8_N14; Fanout = 2; COMB Node = 'baud:inst\|Add0~2103'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { baud:inst|Add0~2101 baud:inst|Add0~2103 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.851 ns baud:inst\|Add0~2105 26 COMB LCCOMB_X35_Y8_N16 2 " "Info: 26: + IC(0.000 ns) + CELL(0.071 ns) = 2.851 ns; Loc. = LCCOMB_X35_Y8_N16; Fanout = 2; COMB Node = 'baud:inst\|Add0~2105'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2103 baud:inst|Add0~2105 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.922 ns baud:inst\|Add0~2107 27 COMB LCCOMB_X35_Y8_N18 2 " "Info: 27: + IC(0.000 ns) + CELL(0.071 ns) = 2.922 ns; Loc. = LCCOMB_X35_Y8_N18; Fanout = 2; COMB Node = 'baud:inst\|Add0~2107'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2105 baud:inst|Add0~2107 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.993 ns baud:inst\|Add0~2109 28 COMB LCCOMB_X35_Y8_N20 2 " "Info: 28: + IC(0.000 ns) + CELL(0.071 ns) = 2.993 ns; Loc. = LCCOMB_X35_Y8_N20; Fanout = 2; COMB Node = 'baud:inst\|Add0~2109'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2107 baud:inst|Add0~2109 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.064 ns baud:inst\|Add0~2111 29 COMB LCCOMB_X35_Y8_N22 2 " "Info: 29: + IC(0.000 ns) + CELL(0.071 ns) = 3.064 ns; Loc. = LCCOMB_X35_Y8_N22; Fanout = 2; COMB Node = 'baud:inst\|Add0~2111'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2109 baud:inst|Add0~2111 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.135 ns baud:inst\|Add0~2113 30 COMB LCCOMB_X35_Y8_N24 2 " "Info: 30: + IC(0.000 ns) + CELL(0.071 ns) = 3.135 ns; Loc. = LCCOMB_X35_Y8_N24; Fanout = 2; COMB Node = 'baud:inst\|Add0~2113'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2111 baud:inst|Add0~2113 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.206 ns baud:inst\|Add0~2115 31 COMB LCCOMB_X35_Y8_N26 2 " "Info: 31: + IC(0.000 ns) + CELL(0.071 ns) = 3.206 ns; Loc. = LCCOMB_X35_Y8_N26; Fanout = 2; COMB Node = 'baud:inst\|Add0~2115'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { baud:inst|Add0~2113 baud:inst|Add0~2115 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 3.616 ns baud:inst\|Add0~2116 32 COMB LCCOMB_X35_Y8_N28 1 " "Info: 32: + IC(0.000 ns) + CELL(0.410 ns) = 3.616 ns; Loc. = LCCOMB_X35_Y8_N28; Fanout = 1; COMB Node = 'baud:inst\|Add0~2116'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { baud:inst|Add0~2115 baud:inst|Add0~2116 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.727 ns) + CELL(0.275 ns) 4.618 ns baud:inst\|Add0~2141 33 COMB LCCOMB_X34_Y9_N12 1 " "Info: 33: + IC(0.727 ns) + CELL(0.275 ns) = 4.618 ns; Loc. = LCCOMB_X34_Y9_N12; Fanout = 1; COMB Node = 'baud:inst\|Add0~2141'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.002 ns" { baud:inst|Add0~2116 baud:inst|Add0~2141 } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 4.702 ns baud:inst\|cnt\[30\] 34 REG LCFF_X34_Y9_N13 3 " "Info: 34: + IC(0.000 ns) + CELL(0.084 ns) = 4.702 ns; Loc. = LCFF_X34_Y9_N13; Fanout = 3; REG Node = 'baud:inst\|cnt\[30\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { baud:inst|Add0~2141 baud:inst|cnt[30] } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.472 ns ( 73.84 % ) " "Info: Total cell delay = 3.472 ns ( 73.84 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.230 ns ( 26.16 % ) " "Info: Total interconnect delay = 1.230 ns ( 26.16 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.702 ns" { baud:inst|cnt[0] baud:inst|Add0~2057 baud:inst|Add0~2059 baud:inst|Add0~2061 baud:inst|Add0~2063 baud:inst|Add0~2065 baud:inst|Add0~2067 baud:inst|Add0~2069 baud:inst|Add0~2071 baud:inst|Add0~2073 baud:inst|Add0~2075 baud:inst|Add0~2077 baud:inst|Add0~2079 baud:inst|Add0~2081 baud:inst|Add0~2083 baud:inst|Add0~2085 baud:inst|Add0~2087 baud:inst|Add0~2089 baud:inst|Add0~2091 baud:inst|Add0~2093 baud:inst|Add0~2095 baud:inst|Add0~2097 baud:inst|Add0~2099 baud:inst|Add0~2101 baud:inst|Add0~2103 baud:inst|Add0~2105 baud:inst|Add0~2107 baud:inst|Add0~2109 baud:inst|Add0~2111 baud:inst|Add0~2113 baud:inst|Add0~2115 baud:inst|Add0~2116 baud:inst|Add0~2141 baud:inst|cnt[30] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.702 ns" { baud:inst|cnt[0] {} baud:inst|Add0~2057 {} baud:inst|Add0~2059 {} baud:inst|Add0~2061 {} baud:inst|Add0~2063 {} baud:inst|Add0~2065 {} baud:inst|Add0~2067 {} baud:inst|Add0~2069 {} baud:inst|Add0~2071 {} baud:inst|Add0~2073 {} baud:inst|Add0~2075 {} baud:inst|Add0~2077 {} baud:inst|Add0~2079 {} baud:inst|Add0~2081 {} baud:inst|Add0~2083 {} baud:inst|Add0~2085 {} baud:inst|Add0~2087 {} baud:inst|Add0~2089 {} baud:inst|Add0~2091 {} baud:inst|Add0~2093 {} baud:inst|Add0~2095 {} baud:inst|Add0~2097 {} baud:inst|Add0~2099 {} baud:inst|Add0~2101 {} baud:inst|Add0~2103 {} baud:inst|Add0~2105 {} baud:inst|Add0~2107 {} baud:inst|Add0~2109 {} baud:inst|Add0~2111 {} baud:inst|Add0~2113 {} baud:inst|Add0~2115 {} baud:inst|Add0~2116 {} baud:inst|Add0~2141 {} baud:inst|cnt[30] {} } { 0.000ns 0.503ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.727ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.275ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.639 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.639 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Uart.bdf" "" { Schematic "E:/My_Design/VHDL/Uart/Uart.bdf" { { 16 -136 32 32 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 32 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 32; COMB Node = 'clk~clkctrl'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "Uart.bdf" "" { Schematic "E:/My_Design/VHDL/Uart/Uart.bdf" { { 16 -136 32 32 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.985 ns) + CELL(0.537 ns) 2.639 ns baud:inst\|cnt\[30\] 3 REG LCFF_X34_Y9_N13 3 " "Info: 3: + IC(0.985 ns) + CELL(0.537 ns) = 2.639 ns; Loc. = LCFF_X34_Y9_N13; Fanout = 3; REG Node = 'baud:inst\|cnt\[30\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.522 ns" { clk~clkctrl baud:inst|cnt[30] } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 58.20 % ) " "Info: Total cell delay = 1.536 ns ( 58.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.103 ns ( 41.80 % ) " "Info: Total interconnect delay = 1.103 ns ( 41.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.639 ns" { clk clk~clkctrl baud:inst|cnt[30] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.639 ns" { clk {} clk~combout {} clk~clkctrl {} baud:inst|cnt[30] {} } { 0.000ns 0.000ns 0.118ns 0.985ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.639 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.639 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Uart.bdf" "" { Schematic "E:/My_Design/VHDL/Uart/Uart.bdf" { { 16 -136 32 32 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 32 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 32; COMB Node = 'clk~clkctrl'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "Uart.bdf" "" { Schematic "E:/My_Design/VHDL/Uart/Uart.bdf" { { 16 -136 32 32 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.985 ns) + CELL(0.537 ns) 2.639 ns baud:inst\|cnt\[0\] 3 REG LCFF_X34_Y9_N19 2 " "Info: 3: + IC(0.985 ns) + CELL(0.537 ns) = 2.639 ns; Loc. = LCFF_X34_Y9_N19; Fanout = 2; REG Node = 'baud:inst\|cnt\[0\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.522 ns" { clk~clkctrl baud:inst|cnt[0] } "NODE_NAME" } } { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 58.20 % ) " "Info: Total cell delay = 1.536 ns ( 58.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.103 ns ( 41.80 % ) " "Info: Total interconnect delay = 1.103 ns ( 41.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.639 ns" { clk clk~clkctrl baud:inst|cnt[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.639 ns" { clk {} clk~combout {} clk~clkctrl {} baud:inst|cnt[0] {} } { 0.000ns 0.000ns 0.118ns 0.985ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.639 ns" { clk clk~clkctrl baud:inst|cnt[30] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.639 ns" { clk {} clk~combout {} clk~clkctrl {} baud:inst|cnt[30] {} } { 0.000ns 0.000ns 0.118ns 0.985ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.639 ns" { clk clk~clkctrl baud:inst|cnt[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.639 ns" { clk {} clk~combout {} clk~clkctrl {} baud:inst|cnt[0] {} } { 0.000ns 0.000ns 0.118ns 0.985ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 19 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 19 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.702 ns" { baud:inst|cnt[0] baud:inst|Add0~2057 baud:inst|Add0~2059 baud:inst|Add0~2061 baud:inst|Add0~2063 baud:inst|Add0~2065 baud:inst|Add0~2067 baud:inst|Add0~2069 baud:inst|Add0~2071 baud:inst|Add0~2073 baud:inst|Add0~2075 baud:inst|Add0~2077 baud:inst|Add0~2079 baud:inst|Add0~2081 baud:inst|Add0~2083 baud:inst|Add0~2085 baud:inst|Add0~2087 baud:inst|Add0~2089 baud:inst|Add0~2091 baud:inst|Add0~2093 baud:inst|Add0~2095 baud:inst|Add0~2097 baud:inst|Add0~2099 baud:inst|Add0~2101 baud:inst|Add0~2103 baud:inst|Add0~2105 baud:inst|Add0~2107 baud:inst|Add0~2109 baud:inst|Add0~2111 baud:inst|Add0~2113 baud:inst|Add0~2115 baud:inst|Add0~2116 baud:inst|Add0~2141 baud:inst|cnt[30] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.702 ns" { baud:inst|cnt[0] {} baud:inst|Add0~2057 {} baud:inst|Add0~2059 {} baud:inst|Add0~2061 {} baud:inst|Add0~2063 {} baud:inst|Add0~2065 {} baud:inst|Add0~2067 {} baud:inst|Add0~2069 {} baud:inst|Add0~2071 {} baud:inst|Add0~2073 {} baud:inst|Add0~2075 {} baud:inst|Add0~2077 {} baud:inst|Add0~2079 {} baud:inst|Add0~2081 {} baud:inst|Add0~2083 {} baud:inst|Add0~2085 {} baud:inst|Add0~2087 {} baud:inst|Add0~2089 {} baud:inst|Add0~2091 {} baud:inst|Add0~2093 {} baud:inst|Add0~2095 {} baud:inst|Add0~2097 {} baud:inst|Add0~2099 {} baud:inst|Add0~2101 {} baud:inst|Add0~2103 {} baud:inst|Add0~2105 {} baud:inst|Add0~2107 {} baud:inst|Add0~2109 {} baud:inst|Add0~2111 {} baud:inst|Add0~2113 {} baud:inst|Add0~2115 {} baud:inst|Add0~2116 {} baud:inst|Add0~2141 {} baud:inst|cnt[30] {} } { 0.000ns 0.503ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.727ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.275ns 0.084ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.639 ns" { clk clk~clkctrl baud:inst|cnt[30] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.639 ns" { clk {} clk~combout {} clk~clkctrl {} baud:inst|cnt[30] {} } { 0.000ns 0.000ns 0.118ns 0.985ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.639 ns" { clk clk~clkctrl baud:inst|cnt[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.639 ns" { clk {} clk~combout {} clk~clkctrl {} baud:inst|cnt[0] {} } { 0.000ns 0.000ns 0.118ns 0.985ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
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