uart.map.qmsg

用ＦＰＧＡ

{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|Uart\|reciever:inst1\|state 5 " "Info: State machine \"\|Uart\|reciever:inst1\|state\" contains 5 states" {  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 16 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|Uart\|transfer:inst2\|state " "Info: Selected Auto state machine encoding method for state machine \"\|Uart\|transfer:inst2\|state\"" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 18 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|Uart\|transfer:inst2\|state " "Info: Encoding result for state machine \"\|Uart\|transfer:inst2\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "transfer:inst2\|state.x_stop " "Info: Encoded state bit \"transfer:inst2\|state.x_stop\"" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "transfer:inst2\|state.x_shift " "Info: Encoded state bit \"transfer:inst2\|state.x_shift\"" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "transfer:inst2\|state.x_wait " "Info: Encoded state bit \"transfer:inst2\|state.x_wait\"" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "transfer:inst2\|state.x_start " "Info: Encoded state bit \"transfer:inst2\|state.x_start\"" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "transfer:inst2\|state.x_idle " "Info: Encoded state bit \"transfer:inst2\|state.x_idle\"" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart\|transfer:inst2\|state.x_idle 00000 " "Info: State \"\|Uart\|transfer:inst2\|state.x_idle\" uses code string \"00000\"" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart\|transfer:inst2\|state.x_start 00011 " "Info: State \"\|Uart\|transfer:inst2\|state.x_start\" uses code string \"00011\"" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart\|transfer:inst2\|state.x_wait 00101 " "Info: State \"\|Uart\|transfer:inst2\|state.x_wait\" uses code string \"00101\"" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart\|transfer:inst2\|state.x_shift 01001 " "Info: State \"\|Uart\|transfer:inst2\|state.x_shift\" uses code string \"01001\"" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart\|transfer:inst2\|state.x_stop 10001 " "Info: State \"\|Uart\|transfer:inst2\|state.x_stop\" uses code string \"10001\"" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 18 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|Uart\|reciever:inst1\|state " "Info: Selected Auto state machine encoding method for state machine \"\|Uart\|reciever:inst1\|state\"" {  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 16 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|Uart\|reciever:inst1\|state " "Info: Encoding result for state machine \"\|Uart\|reciever:inst1\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "reciever:inst1\|state.r_stop " "Info: Encoded state bit \"reciever:inst1\|state.r_stop\"" {  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "reciever:inst1\|state.r_sample " "Info: Encoded state bit \"reciever:inst1\|state.r_sample\"" {  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "reciever:inst1\|state.r_wait " "Info: Encoded state bit \"reciever:inst1\|state.r_wait\"" {  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "reciever:inst1\|state.r_center " "Info: Encoded state bit \"reciever:inst1\|state.r_center\"" {  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "reciever:inst1\|state.r_start " "Info: Encoded state bit \"reciever:inst1\|state.r_start\"" {  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart\|reciever:inst1\|state.r_start 00000 " "Info: State \"\|Uart\|reciever:inst1\|state.r_start\" uses code string \"00000\"" {  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart\|reciever:inst1\|state.r_center 00011 " "Info: State \"\|Uart\|reciever:inst1\|state.r_center\" uses code string \"00011\"" {  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart\|reciever:inst1\|state.r_wait 00101 " "Info: State \"\|Uart\|reciever:inst1\|state.r_wait\" uses code string \"00101\"" {  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart\|reciever:inst1\|state.r_sample 01001 " "Info: State \"\|Uart\|reciever:inst1\|state.r_sample\" uses code string \"01001\"" {  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart\|reciever:inst1\|state.r_stop 10001 " "Info: State \"\|Uart\|reciever:inst1\|state.r_stop\" uses code string \"10001\"" {  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 16 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 26 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "transfer:inst2\|xcnt16\[4\] data_in GND " "Warning (14130): Reduced register \"transfer:inst2\|xcnt16\[4\]\" with stuck data_in port to stuck value GND" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 26 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Critical Warning" "WFTM_FTM_POWER_UP_HIGH_IGNORED_GROUP" "" "Critical Warning: Ignored Power-Up Level option on the following registers" { { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "baud:inst\|cnt\[31\] Low " "Critical Warning: Register baud:inst\|cnt\[31\] will power up to Low" {  } { { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 19 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "baud:inst\|cnt\[0\] Low " "Critical Warning: Register baud:inst\|cnt\[0\] will power up to Low" {  } { { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 19 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0}  } {  } 1 0 "Ignored Power-Up Level option on the following registers" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "257 " "Info: Implemented 257 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "234 " "Info: Implemented 234 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Info: Allocated 163 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 28 15:59:23 2008 " "Info: Processing ended: Thu Feb 28 15:59:23 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}