uart.map.qmsg

用ＦＰＧＡ

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 28 15:59:16 2008 " "Info: Processing started: Thu Feb 28 15:59:16 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Uart -c Uart " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Uart -c Uart" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "baud.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file baud.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 baud-behave " "Info: Found design unit 1: baud-behave" {  } { { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 baud " "Info: Found entity 1: baud" {  } { { "baud.vhd" "" { Text "E:/My_Design/VHDL/Uart/baud.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "transfer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file transfer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 transfer-behave " "Info: Found design unit 1: transfer-behave" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 transfer " "Info: Found entity 1: transfer" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reciever.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reciever.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reciever-behave " "Info: Found design unit 1: reciever-behave" {  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 reciever " "Info: Found entity 1: reciever" {  } { { "reciever.vhd" "" { Text "E:/My_Design/VHDL/Uart/reciever.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Uart.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Uart.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Uart " "Info: Found entity 1: Uart" {  } { { "Uart.bdf" "" { Schematic "E:/My_Design/VHDL/Uart/Uart.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Uart " "Info: Elaborating entity \"Uart\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reciever reciever:inst1 " "Info: Elaborating entity \"reciever\" for hierarchy \"reciever:inst1\"" {  } { { "Uart.bdf" "inst1" { Schematic "E:/My_Design/VHDL/Uart/Uart.bdf" { { 328 352 480 424 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "baud baud:inst " "Info: Elaborating entity \"baud\" for hierarchy \"baud:inst\"" {  } { { "Uart.bdf" "inst" { Schematic "E:/My_Design/VHDL/Uart/Uart.bdf" { { -8 152 248 88 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "transfer transfer:inst2 " "Info: Elaborating entity \"transfer\" for hierarchy \"transfer:inst2\"" {  } { { "Uart.bdf" "inst2" { Schematic "E:/My_Design/VHDL/Uart/Uart.bdf" { { 128 352 512 256 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|Uart\|transfer:inst2\|state 5 " "Info: State machine \"\|Uart\|transfer:inst2\|state\" contains 5 states" {  } { { "transfer.vhd" "" { Text "E:/My_Design/VHDL/Uart/transfer.vhd" 18 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}