adcint.map.eqn

用EP1C系列FPGA控制ADC0809的程序

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-- without limitation, that your use is for the sole purpose of 
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--current_state.st1 is current_state.st1
--operation mode is normal

current_state.st1_lut_out = !current_state.st0;
current_state.st1 = DFFEAS(current_state.st1_lut_out, CLK, VCC, , , , , , );


--current_state.st3 is current_state.st3
--operation mode is normal

current_state.st3_lut_out = current_state.st2 & EOC;
current_state.st3 = DFFEAS(current_state.st3_lut_out, CLK, VCC, , , , , , );


--current_state.st4 is current_state.st4
--operation mode is normal

current_state.st4_lut_out = current_state.st3;
current_state.st4 = DFFEAS(current_state.st4_lut_out, CLK, VCC, , , , , , );


--A1L21 is OE~0
--operation mode is normal

A1L21 = current_state.st3 # current_state.st4;


--REGL[0] is REGL[0]
--operation mode is normal

REGL[0]_lut_out = D[0];
REGL[0] = DFFEAS(REGL[0]_lut_out, current_state.st4, VCC, , , , , , );


--REGL[1] is REGL[1]
--operation mode is normal

REGL[1]_lut_out = D[1];
REGL[1] = DFFEAS(REGL[1]_lut_out, current_state.st4, VCC, , , , , , );


--REGL[2] is REGL[2]
--operation mode is normal

REGL[2]_lut_out = D[2];
REGL[2] = DFFEAS(REGL[2]_lut_out, current_state.st4, VCC, , , , , , );


--REGL[3] is REGL[3]
--operation mode is normal

REGL[3]_lut_out = D[3];
REGL[3] = DFFEAS(REGL[3]_lut_out, current_state.st4, VCC, , , , , , );


--REGL[4] is REGL[4]
--operation mode is normal

REGL[4]_lut_out = D[4];
REGL[4] = DFFEAS(REGL[4]_lut_out, current_state.st4, VCC, , , , , , );


--REGL[5] is REGL[5]
--operation mode is normal

REGL[5]_lut_out = D[5];
REGL[5] = DFFEAS(REGL[5]_lut_out, current_state.st4, VCC, , , , , , );


--REGL[6] is REGL[6]
--operation mode is normal

REGL[6]_lut_out = D[6];
REGL[6] = DFFEAS(REGL[6]_lut_out, current_state.st4, VCC, , , , , , );


--REGL[7] is REGL[7]
--operation mode is normal

REGL[7]_lut_out = D[7];
REGL[7] = DFFEAS(REGL[7]_lut_out, current_state.st4, VCC, , , , , , );


--current_state.st0 is current_state.st0
--operation mode is normal

current_state.st0_lut_out = !current_state.st4;
current_state.st0 = DFFEAS(current_state.st0_lut_out, CLK, VCC, , , , , , );


--current_state.st2 is current_state.st2
--operation mode is normal

current_state.st2_lut_out = current_state.st1 # current_state.st2 & (!EOC);
current_state.st2 = DFFEAS(current_state.st2_lut_out, CLK, VCC, , , , , , );


--CLK is CLK
--operation mode is input

CLK = INPUT();


--EOC is EOC
--operation mode is input

EOC = INPUT();


--D[0] is D[0]
--operation mode is input

D[0] = INPUT();


--D[1] is D[1]
--operation mode is input

D[1] = INPUT();


--D[2] is D[2]
--operation mode is input

D[2] = INPUT();


--D[3] is D[3]
--operation mode is input

D[3] = INPUT();


--D[4] is D[4]
--operation mode is input

D[4] = INPUT();


--D[5] is D[5]
--operation mode is input

D[5] = INPUT();


--D[6] is D[6]
--operation mode is input

D[6] = INPUT();


--D[7] is D[7]
--operation mode is input

D[7] = INPUT();


--ALE is ALE
--operation mode is output

ALE = OUTPUT(current_state.st1);


--START is START
--operation mode is output

START = OUTPUT(current_state.st1);


--OE is OE
--operation mode is output

OE = OUTPUT(A1L21);


--ADDA is ADDA
--operation mode is output

ADDA = OUTPUT(VCC);


--LOCK0 is LOCK0
--operation mode is output

LOCK0 = OUTPUT(current_state.st4);


--Q[0] is Q[0]
--operation mode is output

Q[0] = OUTPUT(REGL[0]);


--Q[1] is Q[1]
--operation mode is output

Q[1] = OUTPUT(REGL[1]);


--Q[2] is Q[2]
--operation mode is output

Q[2] = OUTPUT(REGL[2]);


--Q[3] is Q[3]
--operation mode is output

Q[3] = OUTPUT(REGL[3]);


--Q[4] is Q[4]
--operation mode is output

Q[4] = OUTPUT(REGL[4]);


--Q[5] is Q[5]
--operation mode is output

Q[5] = OUTPUT(REGL[5]);


--Q[6] is Q[6]
--operation mode is output

Q[6] = OUTPUT(REGL[6]);


--Q[7] is Q[7]
--operation mode is output

Q[7] = OUTPUT(REGL[7]);