part5.tan.rpt

基于FPGA的CPU设计 VHDL 编写

+------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 4.324 ns                         ; SW[17]                                                                                                        ; ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg7 ; --         ; CLOCK_50 ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 13.172 ns                        ; ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~portb_address_reg4 ; HEX1[1]                                                                                                      ; CLOCK_50   ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 10.087 ns                        ; SW[17]                                                                                                        ; LEDG[0]                                                                                                      ; --         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 0.359 ns                         ; SW[4]                                                                                                         ; ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg4 ; --         ; CLOCK_50 ; 0            ;
; Clock Setup: 'CLOCK_50'      ; N/A   ; None          ; 216.59 MHz ( period = 4.617 ns ) ; count[14]                                                                                                     ; read_addr[0]                                                                                                 ; CLOCK_50   ; CLOCK_50 ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                                               ;                                                                                                              ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLOCK_50        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+