_primary.vhd

来自「脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systo」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity demo_2_8 is
    port(
        clk             : in     vl_logic;
        ai              : in     vl_logic_vector(7 downto 0);
        gi              : in     vl_logic_vector(7 downto 0);
        bi              : in     vl_logic_vector(15 downto 0);
        ctrl            : in     vl_logic;
        pi              : in     vl_logic_vector(14 downto 0);
        ao              : out    vl_logic_vector(7 downto 0);
        go              : out    vl_logic_vector(7 downto 0);
        po              : out    vl_logic_vector(7 downto 0)
    );
end demo_2_8;