_primary.vhd

来自「脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systo」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity and_xor_7 is
    port(
        ctrl            : in     vl_logic;
        il              : in     vl_logic_vector(6 downto 0);
        ih              : in     vl_logic_vector(6 downto 0);
        o               : out    vl_logic_vector(6 downto 0)
    );
end and_xor_7;