_primary.vhd

来自「脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systo」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity block8s is
    port(
        ai              : in     vl_logic_vector(7 downto 0);
        bi              : in     vl_logic_vector(7 downto 0);
        gi              : in     vl_logic_vector(7 downto 0);
        ti1             : in     vl_logic_vector(7 downto 0);
        ti2             : in     vl_logic_vector(7 downto 0);
        ti3             : in     vl_logic_vector(7 downto 1);
        ao              : out    vl_logic_vector(7 downto 0);
        go              : out    vl_logic_vector(7 downto 0);
        to1             : out    vl_logic_vector(7 downto 0);
        to2             : out    vl_logic_vector(6 downto 0)
    );
end block8s;