_primary.vhd

来自「脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systo」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity mutiplier is
    port(
        clk             : in     vl_logic;
        a               : in     vl_logic_vector(255 downto 0);
        b               : in     vl_logic_vector(255 downto 0);
        m_req           : in     vl_logic_vector(1 downto 0);
        l_req           : in     vl_logic_vector(1 downto 0);
        start           : in     vl_logic;
        over            : out    vl_logic;
        result          : out    vl_logic_vector(255 downto 0)
    );
end mutiplier;