demo_8_32.v

脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systolic）的乘法器

//////////////////////////////////////////////////////////////////////////////////////
//	Name          8*32 bit systolic multiplier                                       //
//	Version       1.0																															  //
//	Author        Marko, Karl                                                       //
//	Date          Dec 23																														//
//	Character     Demo version discribed as in fig 11                               //
//	Changes       Original Version                                                  //
//////////////////////////////////////////////////////////////////////////////////////

module demo_8_32 (clk, Ai, Gi, Bi, ctrl, Pi, Ao, Go, Po);

input  [31:0] Ai, Gi;
input  [255:0] Bi;
input  [62:0] Pi;
input         clk, ctrl;
output [31:0] Ao, Go, Po;
       
reg    [31:0] Ao, Go, Po;

wire   [31:0] ma7, ma6, ma5, ma4, ma3, ma2, ma1, ma0;  // wire for connecting singal A

wire   [31:0] mg7, mg6, mg5, mg4, mg3, mg2, mg1, mg0;  // wire for connecting singal G

wire   [30:0] zp;  // wire for Po[30:0]

wire   [62:0] mp7, mp6, mp5, mp4, mp3, mp2, mp1, mp0;  // wire for connecting singal P

wire          mc7, mc6, mc5, mc4, mc3, mc2, mc1, mc0;  // wire for connecting singal ctrl

reg   [31:0] xa7, xa6, xa5, xa4, xa3, xa2, xa1, xa0;  // reg for connecting singal A       

reg   [31:0] xg7, xg6, xg5, xg4, xg3, xg2, xg1, xg0;  // reg for connecting singal G

reg   [62:0] xp7, xp6, xp5, xp4, xp3, xp2, xp1, xp0;  // reg for connecting singal P

reg          xc7, xc6, xc5, xc4, xc3, xc2, xc1, xc0;  // reg for connecting singal ctrl

reg   [30:0] yph; // for ih in and_xor_31 

always @ (posedge clk)
  begin
    xa7 <= ma7; xa6 <= ma6; xa5 <= ma5; xa4 <= ma4; xa3 <= ma3; xa2 <= ma2; xa1 <= ma1; xa0 <= ma0; 

    xg7 <= mg7; xg6 <= mg6; xg5 <= mg5; xg4 <= mg4; xg3 <= mg3; xg2 <= mg2; xg1 <= mg1; xg0 <= mg0; 

    xp7 <= mp7; xp6 <= mp6; xp5 <= mp5; xp4 <= mp4; xp3 <= mp3; xp2 <= mp2; xp1 <= mp1; xp0 <= mp0; 

    xc7 <= mc7; xc6 <= mc6; xc5 <= mc5; xc4 <= mc4; xc3 <= mc3; xc2 <= mc2; xc1 <= mc1; xc0 <= mc0; 
    
    Po[31] <= mp0[0];//mp0[0] output MSB of Po[]
    yph   <= mp0[62:32];
  end

always @ (xa0,xg0,zp)
  begin
    Ao      = xa0; // instead of ya
    Go      = xg0; // instead of yg
    Po[30:0] = zp[30:0];
  end

sys_block_32 u_matrix_7 (.clk(clk), .Ai(Ai), .Bi(Bi[255:224]), .Gi(Gi), .Pi(Pi), .ctrli(ctrl), .Ao(ma7), .Go(mg7), .Po(mp7), .ctrlo(mc7));
sys_block_32 u_matrix_6 (.clk(clk), .Ai(xa7), .Bi(Bi[223:192]), .Gi(xg7), .Pi(xp7), .ctrli(xc7), .Ao(ma6), .Go(mg6), .Po(mp6), .ctrlo(mc6));
sys_block_32 u_matrix_5 (.clk(clk), .Ai(xa6), .Bi(Bi[191:160]), .Gi(xg6), .Pi(xp6), .ctrli(xc6), .Ao(ma5), .Go(mg5), .Po(mp5), .ctrlo(mc5));
sys_block_32 u_matrix_4 (.clk(clk), .Ai(xa5), .Bi(Bi[159:128]), .Gi(xg5), .Pi(xp5), .ctrli(xc5), .Ao(ma4), .Go(mg4), .Po(mp4), .ctrlo(mc4));
sys_block_32 u_matrix_3 (.clk(clk), .Ai(xa4), .Bi(Bi[127:96]),  .Gi(xg4), .Pi(xp4), .ctrli(xc4), .Ao(ma3), .Go(mg3), .Po(mp3), .ctrlo(mc3));
sys_block_32 u_matrix_2 (.clk(clk), .Ai(xa3), .Bi(Bi[95:64]),   .Gi(xg3), .Pi(xp3), .ctrli(xc3), .Ao(ma2), .Go(mg2), .Po(mp2), .ctrlo(mc2));
sys_block_32 u_matrix_1 (.clk(clk), .Ai(xa2), .Bi(Bi[63:32]),   .Gi(xg2), .Pi(xp2), .ctrli(xc2), .Ao(ma1), .Go(mg1), .Po(mp1), .ctrlo(mc1));
sys_block_32 u_matrix_0 (.clk(clk), .Ai(xa1), .Bi(Bi[31:0]),    .Gi(xg1), .Pi(xp1), .ctrli(xc1), .Ao(ma0), .Go(mg0), .Po(mp0), .ctrlo(mc0));

and_xor_31   u_array_op (.ctrl(mc0), .il(mp0[31:1]), .ih(yph[30:0]), .o(zp));

endmodule