and_2_32.v

来自「脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systo」· Verilog 代码 · 共 50 行

//////////////////////////////////////////////////////////////////////////////////////
//	Name          2*32 inputs and array                                             //
//	Version       1.0																															  //
//	Author        Marko, Karl																												//
//	Date          Dec 23																														//
//	Character     a 2*32 inputs and array                                           //
//	Changes       Original Version                                                  //
//////////////////////////////////////////////////////////////////////////////////////

module and_2_32 (i1, i2, o);
input  [31:0] i1;
input         i2;
output [31:0] o;
wire   [31:0] o;

assign o[ 0] = i1[ 0] & i2;
assign o[ 1] = i1[ 1] & i2;
assign o[ 2] = i1[ 2] & i2;
assign o[ 3] = i1[ 3] & i2;
assign o[ 4] = i1[ 4] & i2;
assign o[ 5] = i1[ 5] & i2;
assign o[ 6] = i1[ 6] & i2;
assign o[ 7] = i1[ 7] & i2;
assign o[ 8] = i1[ 8] & i2;
assign o[ 9] = i1[ 9] & i2;
assign o[10] = i1[10] & i2;
assign o[11] = i1[11] & i2;
assign o[12] = i1[12] & i2;
assign o[13] = i1[13] & i2;
assign o[14] = i1[14] & i2;
assign o[15] = i1[15] & i2;
assign o[16] = i1[16] & i2;
assign o[17] = i1[17] & i2;
assign o[18] = i1[18] & i2;
assign o[19] = i1[19] & i2;
assign o[20] = i1[20] & i2;
assign o[21] = i1[21] & i2;
assign o[22] = i1[22] & i2;
assign o[23] = i1[23] & i2;
assign o[24] = i1[24] & i2;
assign o[25] = i1[25] & i2;
assign o[26] = i1[26] & i2;
assign o[27] = i1[27] & i2;
assign o[28] = i1[28] & i2;
assign o[29] = i1[29] & i2;
assign o[30] = i1[30] & i2;
assign o[31] = i1[31] & i2;

endmodule