demo_16_16.v

脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systolic）的乘法器

//////////////////////////////////////////////////////////////////////////////////////
//	Name          16*16 bit systolic multiplier                                       //
//	Version       1.0																															  //
//	Author        Marko, Karl                                                       //
//	Date          Dec 24																														//
//	Character     Demo version discribed as in fig 11                               //
//	Changes       Original Version                                                  //
//////////////////////////////////////////////////////////////////////////////////////

module demo_16_16 (clk, Ai, Gi, Bi, ctrl, Pi, Ao, Go, Po);

input  [15:0] Ai, Gi;
input  [255:0] Bi;
input  [30:0] Pi;
input         clk, ctrl;
output [15:0] Ao, Go, Po;
       
reg    [15:0] Ao, Go, Po;

wire   [15:0] ma15, ma14, ma13, ma12, ma11, ma10, ma09, ma08; 
wire   [15:0] ma07, ma06, ma05, ma04, ma03, ma02, ma01, ma00;  // wire for connecting singal A

wire   [15:0] mg15, mg14, mg13, mg12, mg11, mg10, mg09, mg08; 
wire   [15:0] mg07, mg06, mg05, mg04, mg03, mg02, mg01, mg00;  // wire for connecting singal G

wire   [14:0] zp;  // wire for Po[14:0]

wire   [30:0] mp15, mp14, mp13, mp12, mp11, mp10, mp09, mp08; 
wire   [30:0] mp07, mp06, mp05, mp04, mp03, mp02, mp01, mp00;  // wire for connecting singal P

wire          mc15, mc14, mc13, mc12, mc11, mc10, mc09, mc08;
wire          mc07, mc06, mc05, mc04, mc03, mc02, mc01, mc00;  // wire for connecting singal ctrl
 
reg   [15:0] xa15, xa14, xa13, xa12, xa11, xa10, xa09, xa08;
reg   [15:0] xa07, xa06, xa05, xa04, xa03, xa02, xa01, xa00;  // reg for connecting singal A
  
reg   [15:0] xg15, xg14, xg13, xg12, xg11, xg10, xg09, xg08;       
reg   [15:0] xg07, xg06, xg05, xg04, xg03, xg02, xg01, xg00;  // reg for connecting singal G

reg   [30:0] xp15, xp14, xp13, xp12, xp11, xp10, xp09, xp08;
reg   [30:0] xp07, xp06, xp05, xp04, xp03, xp02, xp01;        // reg for connecting singal P
 
reg          xc15, xc14, xc13, xc12, xc11, xc10, xc09, xc08; 
reg          xc07, xc06, xc05, xc04, xc03, xc02, xc01;        // reg for connecting singal ctrl

reg   [14:0] yph; // for ih in and_xor_15 

always @ (posedge clk)
  begin
    xa15 <= ma15; xa14 <= ma14; xa13 <= ma13; xa12 <= ma12; 
    xa11 <= ma11; xa10 <= ma10; xa09 <= ma09; xa08 <= ma08; 
    xa07 <= ma07; xa06 <= ma06; xa05 <= ma05; xa04 <= ma04; 
    xa03 <= ma03; xa02 <= ma02; xa01 <= ma01; xa00 <= ma00; 

    xg15 <= mg15; xg14 <= mg14; xg13 <= mg13; xg12 <= mg12; 
    xg11 <= mg11; xg10 <= mg10; xg09 <= mg09; xg08 <= mg08; 
    xg07 <= mg07; xg06 <= mg06; xg05 <= mg05; xg04 <= mg04; 
    xg03 <= mg03; xg02 <= mg02; xg01 <= mg01; xg00 <= mg00; 

    xp15 <= mp15; xp14 <= mp14; xp13 <= mp13; xp12 <= mp12; 
    xp11 <= mp11; xp10 <= mp10; xp09 <= mp09; xp08 <= mp08; 
    xp07 <= mp07; xp06 <= mp06; xp05 <= mp05; xp04 <= mp04; 
    xp03 <= mp03; xp02 <= mp02; xp01 <= mp01; 


    xc15 <= mc15; xc14 <= mc14; xc13 <= mc13; xc12 <= mc12; 
    xc11 <= mc11; xc10 <= mc10; xc09 <= mc09; xc08 <= mc08; 
    xc07 <= mc07; xc06 <= mc06; xc05 <= mc05; xc04 <= mc04; 
    xc03 <= mc03; xc02 <= mc02; xc01 <= mc01;  

    
    Po[15] <= mp00[0];//mp00[0] output MSB of Po[]
    yph   <= mp00[30:16];
  end

always @ (xa00,xg00,zp)
  begin
    Ao      = xa00; // instead of ya
    Go      = xg00; // instead of yg
    Po[14:0] = zp[14:0];
  end

sys_block_16 u_matrix_15 (.clk(clk), .Ai(Ai),   .Bi(Bi[255:240]), .Gi(Gi),   .Pi(Pi),   .ctrli(ctrl), .Ao(ma15), .Go(mg15), .Po(mp15), .ctrlo(mc15));
sys_block_16 u_matrix_14 (.clk(clk), .Ai(xa15), .Bi(Bi[239:224]), .Gi(xg15), .Pi(xp15), .ctrli(xc15), .Ao(ma14), .Go(mg14), .Po(mp14), .ctrlo(mc14));
sys_block_16 u_matrix_13 (.clk(clk), .Ai(xa14), .Bi(Bi[223:208]), .Gi(xg14), .Pi(xp14), .ctrli(xc14), .Ao(ma13), .Go(mg13), .Po(mp13), .ctrlo(mc13));
sys_block_16 u_matrix_12 (.clk(clk), .Ai(xa13), .Bi(Bi[207:192]), .Gi(xg13), .Pi(xp13), .ctrli(xc13), .Ao(ma12), .Go(mg12), .Po(mp12), .ctrlo(mc12));
sys_block_16 u_matrix_11 (.clk(clk), .Ai(xa12), .Bi(Bi[191:176]), .Gi(xg12), .Pi(xp12), .ctrli(xc12), .Ao(ma11), .Go(mg11), .Po(mp11), .ctrlo(mc11));
sys_block_16 u_matrix_10 (.clk(clk), .Ai(xa11), .Bi(Bi[175:160]), .Gi(xg11), .Pi(xp11), .ctrli(xc11), .Ao(ma10), .Go(mg10), .Po(mp10), .ctrlo(mc10));
sys_block_16 u_matrix_09 (.clk(clk), .Ai(xa10), .Bi(Bi[159:144]), .Gi(xg10), .Pi(xp10), .ctrli(xc10), .Ao(ma09), .Go(mg09), .Po(mp09), .ctrlo(mc09));
sys_block_16 u_matrix_08 (.clk(clk), .Ai(xa09), .Bi(Bi[143:128]), .Gi(xg09), .Pi(xp09), .ctrli(xc09), .Ao(ma08), .Go(mg08), .Po(mp08), .ctrlo(mc08));
sys_block_16 u_matrix_07 (.clk(clk), .Ai(xa08), .Bi(Bi[127:112]), .Gi(xg08), .Pi(xp08), .ctrli(xc08), .Ao(ma07), .Go(mg07), .Po(mp07), .ctrlo(mc07));
sys_block_16 u_matrix_06 (.clk(clk), .Ai(xa07), .Bi(Bi[111:96]),  .Gi(xg07), .Pi(xp07), .ctrli(xc07), .Ao(ma06), .Go(mg06), .Po(mp06), .ctrlo(mc06));
sys_block_16 u_matrix_05 (.clk(clk), .Ai(xa06), .Bi(Bi[95:80]),   .Gi(xg06), .Pi(xp06), .ctrli(xc06), .Ao(ma05), .Go(mg05), .Po(mp05), .ctrlo(mc05));
sys_block_16 u_matrix_04 (.clk(clk), .Ai(xa05), .Bi(Bi[79:64]),   .Gi(xg05), .Pi(xp05), .ctrli(xc05), .Ao(ma04), .Go(mg04), .Po(mp04), .ctrlo(mc04));
sys_block_16 u_matrix_03 (.clk(clk), .Ai(xa04), .Bi(Bi[63:48]),   .Gi(xg04), .Pi(xp04), .ctrli(xc04), .Ao(ma03), .Go(mg03), .Po(mp03), .ctrlo(mc03));
sys_block_16 u_matrix_02 (.clk(clk), .Ai(xa03), .Bi(Bi[47:32]),   .Gi(xg03), .Pi(xp03), .ctrli(xc03), .Ao(ma02), .Go(mg02), .Po(mp02), .ctrlo(mc02));
sys_block_16 u_matrix_01 (.clk(clk), .Ai(xa02), .Bi(Bi[31:16]),   .Gi(xg02), .Pi(xp02), .ctrli(xc02), .Ao(ma01), .Go(mg01), .Po(mp01), .ctrlo(mc01));
sys_block_16 u_matrix_00 (.clk(clk), .Ai(xa01), .Bi(Bi[15:0]),    .Gi(xg01), .Pi(xp01), .ctrli(xc01), .Ao(ma00), .Go(mg00), .Po(mp00), .ctrlo(mc00));

and_xor_15   u_array_op (.ctrl(mc00), .il(mp00[15:1]), .ih(yph[14:0]), .o(zp));

endmodule