block8_systolic.v

来自「脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systo」· Verilog 代码 · 共 55 行

//////////////////////////////////////////////////////////////////////////////////////
//	Name          8 bit block used in systolic array                                //
//	Version       1.0																															  //
//	Author        Marko, Karl                                                       //
//	Date          Dec 22																														//
//	Character     discribed as in fig 9                                             //
//	Changes       Original Version                                                  //
//////////////////////////////////////////////////////////////////////////////////////

module sys_block_8 (clk, Ai, Bi, Gi, Pi, ctrli, Ao, Go, Po, ctrlo);

input  [ 7:0] Ai, Bi, Gi;
input  [14:0] Pi;
input         ctrli, clk;
output [ 7:0] Ao, Go;
output [14:0] Po;
output        ctrlo;

reg    [ 7:0] Ao, Go;
reg           ctrlo;
wire   [14:0] Po;

wire   [ 7:0] wp, wg, wa, wh;
wire   [ 7:0] ws;
wire   [ 6:0] wr;   
reg    [ 7:0] wt;
reg    [ 6:0] Poh;

always @ (posedge clk)
  begin
    wt [7:0] <= wh[7:0];
    ctrlo    <= ctrli;
    Go [7:0] <= wg[7:0];
    Ao [7:0] <= wa[7:0];
    Poh[6:0] <= wr[6:0];
  end

Block8s u_matrix_block8 (.ai(Ai), .bi(Bi), .gi(Gi), .ti1({wt[7], wh[6:0]}), .ti2(wp), .ti3(Pi[14:8]), .ao(wa), .go(wg), .to1(ws), .to2(wr));

mux_2 u_mux_1 (.ctrl(ctrli), .i0(Pi[0]), .i1(wt[7]), .o(wh[7]));
mux_2 u_mux_2 (.ctrl(ctrlo), .i0(ws[7]), .i1(wt[6]), .o(wh[6]));
mux_2 u_mux_3 (.ctrl(ctrlo), .i0(ws[6]), .i1(wt[5]), .o(wh[5]));
mux_2 u_mux_4 (.ctrl(ctrlo), .i0(ws[5]), .i1(wt[4]), .o(wh[4]));
mux_2 u_mux_5 (.ctrl(ctrlo), .i0(ws[4]), .i1(wt[3]), .o(wh[3]));
mux_2 u_mux_6 (.ctrl(ctrlo), .i0(ws[3]), .i1(wt[2]), .o(wh[2]));
mux_2 u_mux_7 (.ctrl(ctrlo), .i0(ws[2]), .i1(wt[1]), .o(wh[1]));
mux_2 u_mux_8 (.ctrl(ctrlo), .i0(ws[1]), .i1(wt[0]), .o(wh[0]));

and_2_8 u_and_array (.i1(Pi[7:0]), .i2(ctrli), .o(wp[7:0]));

assign Po[ 7:0] = ws[7:0];
assign Po[14:8] = Poh[6:0];

endmodule