multiplier.v

来自「booth乘法器：&#61550 16*16有符号乘法器」· Verilog 代码 · 共 35 行

module multiplier(x,y,p);
    input [15:0] x;
    input [15:0] y;
    output [31:0] p;
    wire [31:0] p;
    wire [16:0] a;
    wire [16:0] b;
    wire [16:0] c;
    wire [16:0] d;
    wire [16:0] e;
    wire [16:0] f;
    wire [16:0] g;
    wire [16:0] h;
    /*reg y1;
    reg y3;
    reg y5;
    reg y7;
    reg y9;
    reg y11;
    reg y13;
    reg y15;*/
    booth booth1(x,{y[1:0],1'b0},a,y1);
    booth booth2(x,y[3:1],b,y3);
    booth booth3(x,y[5:3],c,y5);
    booth booth4(x,y[7:5],d,y7);
    booth booth5(x,y[9:7],e,y9);
    booth booth6(x,y[11:9],f,y11);
    booth booth7(x,y[13:11],g,y13);
    booth booth8(x,y[15:13],h,y15);
    add add1(a,b,c,d,e,f,g,h,y1,y3,y5,y7,y9,y11,y13,y15,p);
endmodule