alu.v

来自「4bit ALU（运算逻辑单元）的设计 给出了此次设计alu的输入输出结构及相」· Verilog 代码 · 共 148 行

//`timescale 1ns/1ps

module alu_test;
    reg [3:0] op = 4'b0001;
    reg [31:0] s1 = 32'h0000_0000;
    reg [31:0] s2 = 32'h0000_0000;
    reg [31:0] imm_32 = 32'h0000_0000;
    reg imm_en = 1'b0;
    wire [31:0] alu_o;
    wire [4:0] flag_o;
    reg [1:0] mux_1 = 2'b00;
    reg [1:0] mux_2 = 2'b00;
    reg [31:0] fdata_ex = 32'h0000_0000;
    reg [31:0] fdata_mem = 32'h0000_0000;
    wire [31:0] s2_fwd;
    reg c_in = 1'b0;

    
    alu UUT (
        .op(op),
        .s1(s1),
        .s2(s2),
        .imm_32(imm_32),
        .imm_en(imm_en),
        .alu_o(alu_o),
        .flag_o(flag_o),
        .mux_1(mux_1),
        .mux_2(mux_2),
        .fdata_ex(fdata_ex),
        .fdata_mem(fdata_mem),
        .s2_fwd(s2_fwd),
        .c_in(c_in));

    initial begin
    	#50;
        s1 = 32'h0000_0001;
        s2 = 32'h0000_0004;
        op = 4'h1;
        c_in = 1'b0;
     #50;
        s1 = 32'hffff_ffff;
        s2 = 32'hffff_ffff;
        op = 4'h1;
        c_in = 1'b0;
    	#50;
        s1 = 32'h7fff_ffff;
        s2 = 32'h0000_0001;
        op = 4'h1;
        c_in = 1'b0;
     #50;
        s1 = 32'hffff_fff0;
        s2 = 32'h0000_00ff;
        op = 4'h1;
        c_in = 1'b0;
   	 #50;
        s1 = 32'h0000_0001;
        s2 = 32'h0000_0004;
        op = 4'h3;
        c_in = 1'b1;
     #50;
        s1 = 32'h0000_0004;
        s2 = 32'h0000_0001;
        op = 4'h3;
        c_in = 1'b1;
 	  #50;
        s1 = 32'hffff_ffff;
        s2 = 32'h0000_000f;
        op = 4'h3;
        c_in = 1'b1;
     #50;
        s1 = 32'h0000_0004;
        s2 = 32'h0000_0002;
        op = 4'h3;
        c_in = 1'b1;
 	  #50;
        s1 = 32'h0000_0001;
        s2 = 32'h0000_0001;
        op = 4'h3;
        c_in = 1'b1;
     #50;
        s1 = 32'h0000_0004;
        s2 = 32'h0000_0002;
        op = 4'h4;
        c_in = 1'b0;
 	  #50;
        s1 = 32'h0000_0004;
        s2 = 32'h0000_0002;
        op = 4'h4;
        c_in = 1'b1;
     #50;
        s1 = 32'h0000_0001;
        s2 = 32'h0000_0001;
        op = 4'h4;
        c_in = 1'b0;
  	  #50;
        s1 = 32'h0000_0001;
        s2 = 32'h0000_0001;
        op = 4'h4;
        c_in = 1'b1;
     #50;
        s1 = 32'h0000_0001;
        s2 = 32'h0000_0001;
        op = 4'h1;
        c_in = 1'b1;
        imm_32 = 32'h0000_00ff;
        imm_en = 1'b1;
     #50;
        s1 = 32'h0000_0001;
        s2 = 32'h0000_0001;
        op = 4'h1;
        c_in = 1'b1;
        imm_32 = 32'h0000_0000;
        imm_en = 1'b0;
        mux_1 = 2'b01;
        mux_2 = 2'b01;
        fdata_ex = 32'h0000_0002;
        fdata_mem = 32'h0000_0003;
     #50;
        s1 = 32'h0000_0001;
        s2 = 32'h0000_0001;
        op = 4'h1;
        c_in = 1'b1;
        imm_32 = 32'h0000_0000;
        imm_en = 1'b0;
        mux_1 = 2'b01;
        mux_2 = 2'b10;
        fdata_ex = 32'h0000_0002;
        fdata_mem = 32'h0000_0003;
     #50;
        s1 = 32'h0000_0001;
        s2 = 32'h0000_0001;
        op = 4'h1;
        c_in = 1'b1;
        imm_32 = 32'h0000_0000;
        imm_en = 1'b0;
        mux_1 = 2'b10;
        mux_2 = 2'b10;
        fdata_ex = 32'h0000_0002;
        fdata_mem = 32'h0000_0003;
     #50;
        s1 = 32'h0000_0001;
        s2 = 32'h0000_0001;
        op = 4'h1;
        c_in = 1'b1;
    end
    
endmodule