mypinlvji.map.qmsg

该程序实现一个频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 28 14:55:14 2008 " "Info: Processing started: Wed May 28 14:55:14 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mypinlvji -c mypinlvji " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mypinlvji -c mypinlvji" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mypinlvji.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file mypinlvji.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 mypinlvji " "Info: Found entity 1: mypinlvji" {  } { { "mypinlvji.bdf" "" { Schematic "E:/Altera/myvhdl/mypinlvji/mypinlvji.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pinlvji.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pinlvji.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pinlvji-one " "Info: Found design unit 1: pinlvji-one" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pinlvji " "Info: Found entity 1: pinlvji" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int_div.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file int_div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 int_div-behav " "Info: Found design unit 1: int_div-behav" {  } { { "int_div.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/int_div.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 int_div " "Info: Found entity 1: int_div" {  } { { "int_div.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/int_div.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "mypinlvji " "Info: Elaborating entity \"mypinlvji\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pinlvji pinlvji:inst1 " "Info: Elaborating entity \"pinlvji\" for hierarchy \"pinlvji:inst1\"" {  } { { "mypinlvji.bdf" "inst1" { Schematic "E:/Altera/myvhdl/mypinlvji/mypinlvji.bdf" { { 96 312 448 192 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "int_div int_div:inst2 " "Info: Elaborating entity \"int_div\" for hierarchy \"int_div:inst2\"" {  } { { "mypinlvji.bdf" "inst2" { Schematic "E:/Altera/myvhdl/mypinlvji/mypinlvji.bdf" { { 112 152 248 208 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "252 " "Info: Implemented 252 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "236 " "Info: Implemented 236 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "162 " "Info: Allocated 162 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 28 14:55:19 2008 " "Info: Processing ended: Wed May 28 14:55:19 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}