prev_cmp_myshizhong.tan.qmsg

该程序实现一个数字钟

{ "Info" "ITDB_TH_RESULT" "clock:inst\|inc_reg key4 clk 1.472 ns register " "Info: th for register \"clock:inst\|inc_reg\" (data pin = \"key4\", clock pin = \"clk\") is 1.472 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.070 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 9.070 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { -24 -32 136 -8 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.548 ns) + CELL(0.970 ns) 3.658 ns clock:inst\|clk1khz 2 REG LCFF_X18_Y10_N1 3 " "Info: 2: + IC(1.548 ns) + CELL(0.970 ns) = 3.658 ns; Loc. = LCFF_X18_Y10_N1; Fanout = 3; REG Node = 'clock:inst\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clk clock:inst|clk1khz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.406 ns) + CELL(0.970 ns) 6.034 ns clock:inst\|clk1hz 3 REG LCFF_X24_Y11_N9 2 " "Info: 3: + IC(1.406 ns) + CELL(0.970 ns) = 6.034 ns; Loc. = LCFF_X24_Y11_N9; Fanout = 2; REG Node = 'clock:inst\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.376 ns" { clock:inst|clk1khz clock:inst|clk1hz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.523 ns) + CELL(0.000 ns) 7.557 ns clock:inst\|clk1hz~clkctrl 4 COMB CLKCTRL_G4 18 " "Info: 4: + IC(1.523 ns) + CELL(0.000 ns) = 7.557 ns; Loc. = CLKCTRL_G4; Fanout = 18; COMB Node = 'clock:inst\|clk1hz~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.523 ns" { clock:inst|clk1hz clock:inst|clk1hz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.847 ns) + CELL(0.666 ns) 9.070 ns clock:inst\|inc_reg 5 REG LCFF_X24_Y8_N1 2 " "Info: 5: + IC(0.847 ns) + CELL(0.666 ns) = 9.070 ns; Loc. = LCFF_X24_Y8_N1; Fanout = 2; REG Node = 'clock:inst\|inc_reg'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.513 ns" { clock:inst|clk1hz~clkctrl clock:inst|inc_reg } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 41.30 % ) " "Info: Total cell delay = 3.746 ns ( 41.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.324 ns ( 58.70 % ) " "Info: Total interconnect delay = 5.324 ns ( 58.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.070 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|inc_reg } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.070 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|inc_reg {} } { 0.000ns 0.000ns 1.548ns 1.406ns 1.523ns 0.847ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.904 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.904 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns key4 1 PIN PIN_97 2 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_97; Fanout = 2; PIN Node = 'key4'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { key4 } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { 80 -32 136 96 "key4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.178 ns) + CELL(0.624 ns) 7.796 ns clock:inst\|inc_reg~129 2 COMB LCCOMB_X24_Y8_N0 1 " "Info: 2: + IC(6.178 ns) + CELL(0.624 ns) = 7.796 ns; Loc. = LCCOMB_X24_Y8_N0; Fanout = 1; COMB Node = 'clock:inst\|inc_reg~129'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.802 ns" { key4 clock:inst|inc_reg~129 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.904 ns clock:inst\|inc_reg 3 REG LCFF_X24_Y8_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.904 ns; Loc. = LCFF_X24_Y8_N1; Fanout = 2; REG Node = 'clock:inst\|inc_reg'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { clock:inst|inc_reg~129 clock:inst|inc_reg } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.726 ns ( 21.84 % ) " "Info: Total cell delay = 1.726 ns ( 21.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.178 ns ( 78.16 % ) " "Info: Total interconnect delay = 6.178 ns ( 78.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.904 ns" { key4 clock:inst|inc_reg~129 clock:inst|inc_reg } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "7.904 ns" { key4 {} key4~combout {} clock:inst|inc_reg~129 {} clock:inst|inc_reg {} } { 0.000ns 0.000ns 6.178ns 0.000ns } { 0.000ns 0.994ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.070 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|inc_reg } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.070 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|inc_reg {} } { 0.000ns 0.000ns 1.548ns 1.406ns 1.523ns 0.847ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.904 ns" { key4 clock:inst|inc_reg~129 clock:inst|inc_reg } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "7.904 ns" { key4 {} key4~combout {} clock:inst|inc_reg~129 {} clock:inst|inc_reg {} } { 0.000ns 0.000ns 6.178ns 0.000ns } { 0.000ns 0.994ns 0.624ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 28 15:24:52 2008 " "Info: Processing ended: Wed May 28 15:24:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}