prev_cmp_myshizhong.tan.qmsg

该程序实现一个数字钟

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "key3 register register clock:inst\|state\[0\] clock:inst\|state\[1\] 360.1 MHz Internal " "Info: Clock \"key3\" Internal fmax is restricted to 360.1 MHz between source register \"clock:inst\|state\[0\]\" and destination register \"clock:inst\|state\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.755 ns + Longest register register " "Info: + Longest register to register delay is 0.755 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock:inst\|state\[0\] 1 REG LCFF_X25_Y12_N3 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y12_N3; Fanout = 6; REG Node = 'clock:inst\|state\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock:inst|state[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.206 ns) 0.647 ns clock:inst\|state\[1\]~33 2 COMB LCCOMB_X25_Y12_N6 1 " "Info: 2: + IC(0.441 ns) + CELL(0.206 ns) = 0.647 ns; Loc. = LCCOMB_X25_Y12_N6; Fanout = 1; COMB Node = 'clock:inst\|state\[1\]~33'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.647 ns" { clock:inst|state[0] clock:inst|state[1]~33 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.755 ns clock:inst\|state\[1\] 3 REG LCFF_X25_Y12_N7 5 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.755 ns; Loc. = LCFF_X25_Y12_N7; Fanout = 5; REG Node = 'clock:inst\|state\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { clock:inst|state[1]~33 clock:inst|state[1] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 41.59 % ) " "Info: Total cell delay = 0.314 ns ( 41.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.441 ns ( 58.41 % ) " "Info: Total interconnect delay = 0.441 ns ( 58.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.755 ns" { clock:inst|state[0] clock:inst|state[1]~33 clock:inst|state[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "0.755 ns" { clock:inst|state[0] {} clock:inst|state[1]~33 {} clock:inst|state[1] {} } { 0.000ns 0.441ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key3 destination 3.542 ns + Shortest register " "Info: + Shortest clock path from clock \"key3\" to destination register is 3.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns key3 1 CLK PIN_99 2 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_99; Fanout = 2; CLK Node = 'key3'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { key3 } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { 56 -32 136 72 "key3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.892 ns) + CELL(0.666 ns) 3.542 ns clock:inst\|state\[1\] 2 REG LCFF_X25_Y12_N7 5 " "Info: 2: + IC(1.892 ns) + CELL(0.666 ns) = 3.542 ns; Loc. = LCFF_X25_Y12_N7; Fanout = 5; REG Node = 'clock:inst\|state\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.558 ns" { key3 clock:inst|state[1] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.650 ns ( 46.58 % ) " "Info: Total cell delay = 1.650 ns ( 46.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.892 ns ( 53.42 % ) " "Info: Total interconnect delay = 1.892 ns ( 53.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.542 ns" { key3 clock:inst|state[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "3.542 ns" { key3 {} key3~combout {} clock:inst|state[1] {} } { 0.000ns 0.000ns 1.892ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key3 source 3.542 ns - Longest register " "Info: - Longest clock path from clock \"key3\" to source register is 3.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns key3 1 CLK PIN_99 2 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_99; Fanout = 2; CLK Node = 'key3'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { key3 } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { 56 -32 136 72 "key3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.892 ns) + CELL(0.666 ns) 3.542 ns clock:inst\|state\[0\] 2 REG LCFF_X25_Y12_N3 6 " "Info: 2: + IC(1.892 ns) + CELL(0.666 ns) = 3.542 ns; Loc. = LCFF_X25_Y12_N3; Fanout = 6; REG Node = 'clock:inst\|state\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.558 ns" { key3 clock:inst|state[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.650 ns ( 46.58 % ) " "Info: Total cell delay = 1.650 ns ( 46.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.892 ns ( 53.42 % ) " "Info: Total interconnect delay = 1.892 ns ( 53.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.542 ns" { key3 clock:inst|state[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "3.542 ns" { key3 {} key3~combout {} clock:inst|state[0] {} } { 0.000ns 0.000ns 1.892ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.542 ns" { key3 clock:inst|state[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "3.542 ns" { key3 {} key3~combout {} clock:inst|state[1] {} } { 0.000ns 0.000ns 1.892ns } { 0.000ns 0.984ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.542 ns" { key3 clock:inst|state[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "3.542 ns" { key3 {} key3~combout {} clock:inst|state[0] {} } { 0.000ns 0.000ns 1.892ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.755 ns" { clock:inst|state[0] clock:inst|state[1]~33 clock:inst|state[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "0.755 ns" { clock:inst|state[0] {} clock:inst|state[1]~33 {} clock:inst|state[1] {} } { 0.000ns 0.441ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.542 ns" { key3 clock:inst|state[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "3.542 ns" { key3 {} key3~combout {} clock:inst|state[1] {} } { 0.000ns 0.000ns 1.892ns } { 0.000ns 0.984ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.542 ns" { key3 clock:inst|state[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "3.542 ns" { key3 {} key3~combout {} clock:inst|state[0] {} } { 0.000ns 0.000ns 1.892ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock:inst|state[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { clock:inst|state[1] {} } {  } {  } "" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "clock:inst\|hour\[0\] key4 clk 1.949 ns register " "Info: tsu for register \"clock:inst\|hour\[0\]\" (data pin = \"key4\", clock pin = \"clk\") is 1.949 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.077 ns + Longest pin register " "Info: + Longest pin to register delay is 11.077 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns key4 1 PIN PIN_97 2 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_97; Fanout = 2; PIN Node = 'key4'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { key4 } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { 80 -32 136 96 "key4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.181 ns) + CELL(0.370 ns) 7.545 ns clock:inst\|hour\[4\]~184 2 COMB LCCOMB_X24_Y8_N12 3 " "Info: 2: + IC(6.181 ns) + CELL(0.370 ns) = 7.545 ns; Loc. = LCCOMB_X24_Y8_N12; Fanout = 3; COMB Node = 'clock:inst\|hour\[4\]~184'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.551 ns" { key4 clock:inst|hour[4]~184 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.131 ns) + CELL(0.650 ns) 9.326 ns clock:inst\|hour\[4\]~185 3 COMB LCCOMB_X24_Y12_N30 1 " "Info: 3: + IC(1.131 ns) + CELL(0.650 ns) = 9.326 ns; Loc. = LCCOMB_X24_Y12_N30; Fanout = 1; COMB Node = 'clock:inst\|hour\[4\]~185'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.781 ns" { clock:inst|hour[4]~184 clock:inst|hour[4]~185 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.206 ns) 9.897 ns clock:inst\|hour\[4\]~186 4 COMB LCCOMB_X24_Y12_N6 5 " "Info: 4: + IC(0.365 ns) + CELL(0.206 ns) = 9.897 ns; Loc. = LCCOMB_X24_Y12_N6; Fanout = 5; COMB Node = 'clock:inst\|hour\[4\]~186'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { clock:inst|hour[4]~185 clock:inst|hour[4]~186 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.325 ns) + CELL(0.855 ns) 11.077 ns clock:inst\|hour\[0\] 5 REG LCFF_X24_Y12_N9 5 " "Info: 5: + IC(0.325 ns) + CELL(0.855 ns) = 11.077 ns; Loc. = LCFF_X24_Y12_N9; Fanout = 5; REG Node = 'clock:inst\|hour\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { clock:inst|hour[4]~186 clock:inst|hour[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.075 ns ( 27.76 % ) " "Info: Total cell delay = 3.075 ns ( 27.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.002 ns ( 72.24 % ) " "Info: Total interconnect delay = 8.002 ns ( 72.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.077 ns" { key4 clock:inst|hour[4]~184 clock:inst|hour[4]~185 clock:inst|hour[4]~186 clock:inst|hour[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "11.077 ns" { key4 {} key4~combout {} clock:inst|hour[4]~184 {} clock:inst|hour[4]~185 {} clock:inst|hour[4]~186 {} clock:inst|hour[0] {} } { 0.000ns 0.000ns 6.181ns 1.131ns 0.365ns 0.325ns } { 0.000ns 0.994ns 0.370ns 0.650ns 0.206ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.088 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 9.088 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { -24 -32 136 -8 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.548 ns) + CELL(0.970 ns) 3.658 ns clock:inst\|clk1khz 2 REG LCFF_X18_Y10_N1 3 " "Info: 2: + IC(1.548 ns) + CELL(0.970 ns) = 3.658 ns; Loc. = LCFF_X18_Y10_N1; Fanout = 3; REG Node = 'clock:inst\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clk clock:inst|clk1khz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.406 ns) + CELL(0.970 ns) 6.034 ns clock:inst\|clk1hz 3 REG LCFF_X24_Y11_N9 2 " "Info: 3: + IC(1.406 ns) + CELL(0.970 ns) = 6.034 ns; Loc. = LCFF_X24_Y11_N9; Fanout = 2; REG Node = 'clock:inst\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.376 ns" { clock:inst|clk1khz clock:inst|clk1hz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.523 ns) + CELL(0.000 ns) 7.557 ns clock:inst\|clk1hz~clkctrl 4 COMB CLKCTRL_G4 18 " "Info: 4: + IC(1.523 ns) + CELL(0.000 ns) = 7.557 ns; Loc. = CLKCTRL_G4; Fanout = 18; COMB Node = 'clock:inst\|clk1hz~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.523 ns" { clock:inst|clk1hz clock:inst|clk1hz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.865 ns) + CELL(0.666 ns) 9.088 ns clock:inst\|hour\[0\] 5 REG LCFF_X24_Y12_N9 5 " "Info: 5: + IC(0.865 ns) + CELL(0.666 ns) = 9.088 ns; Loc. = LCFF_X24_Y12_N9; Fanout = 5; REG Node = 'clock:inst\|hour\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.531 ns" { clock:inst|clk1hz~clkctrl clock:inst|hour[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 41.22 % ) " "Info: Total cell delay = 3.746 ns ( 41.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.342 ns ( 58.78 % ) " "Info: Total interconnect delay = 5.342 ns ( 58.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.088 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|hour[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.088 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|hour[0] {} } { 0.000ns 0.000ns 1.548ns 1.406ns 1.523ns 0.865ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.077 ns" { key4 clock:inst|hour[4]~184 clock:inst|hour[4]~185 clock:inst|hour[4]~186 clock:inst|hour[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "11.077 ns" { key4 {} key4~combout {} clock:inst|hour[4]~184 {} clock:inst|hour[4]~185 {} clock:inst|hour[4]~186 {} clock:inst|hour[0] {} } { 0.000ns 0.000ns 6.181ns 1.131ns 0.365ns 0.325ns } { 0.000ns 0.994ns 0.370ns 0.650ns 0.206ns 0.855ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.088 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|hour[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.088 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|hour[0] {} } { 0.000ns 0.000ns 1.548ns 1.406ns 1.523ns 0.865ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk 78leddata\[3\] clock:inst\|sec\[5\] 22.272 ns register " "Info: tco from clock \"clk\" to destination pin \"78leddata\[3\]\" through register \"clock:inst\|sec\[5\]\" is 22.272 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.088 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 9.088 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { -24 -32 136 -8 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.548 ns) + CELL(0.970 ns) 3.658 ns clock:inst\|clk1khz 2 REG LCFF_X18_Y10_N1 3 " "Info: 2: + IC(1.548 ns) + CELL(0.970 ns) = 3.658 ns; Loc. = LCFF_X18_Y10_N1; Fanout = 3; REG Node = 'clock:inst\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clk clock:inst|clk1khz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.406 ns) + CELL(0.970 ns) 6.034 ns clock:inst\|clk1hz 3 REG LCFF_X24_Y11_N9 2 " "Info: 3: + IC(1.406 ns) + CELL(0.970 ns) = 6.034 ns; Loc. = LCFF_X24_Y11_N9; Fanout = 2; REG Node = 'clock:inst\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.376 ns" { clock:inst|clk1khz clock:inst|clk1hz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.523 ns) + CELL(0.000 ns) 7.557 ns clock:inst\|clk1hz~clkctrl 4 COMB CLKCTRL_G4 18 " "Info: 4: + IC(1.523 ns) + CELL(0.000 ns) = 7.557 ns; Loc. = CLKCTRL_G4; Fanout = 18; COMB Node = 'clock:inst\|clk1hz~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.523 ns" { clock:inst|clk1hz clock:inst|clk1hz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.865 ns) + CELL(0.666 ns) 9.088 ns clock:inst\|sec\[5\] 5 REG LCFF_X24_Y12_N25 11 " "Info: 5: + IC(0.865 ns) + CELL(0.666 ns) = 9.088 ns; Loc. = LCFF_X24_Y12_N25; Fanout = 11; REG Node = 'clock:inst\|sec\[5\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.531 ns" { clock:inst|clk1hz~clkctrl clock:inst|sec[5] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 41.22 % ) " "Info: Total cell delay = 3.746 ns ( 41.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.342 ns ( 58.78 % ) " "Info: Total interconnect delay = 5.342 ns ( 58.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.088 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|sec[5] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.088 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|sec[5] {} } { 0.000ns 0.000ns 1.548ns 1.406ns 1.523ns 0.865ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.880 ns + Longest register pin " "Info: + Longest register to pin delay is 12.880 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock:inst\|sec\[5\] 1 REG LCFF_X24_Y12_N25 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y12_N25; Fanout = 11; REG Node = 'clock:inst\|sec\[5\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock:inst|sec[5] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.233 ns) + CELL(0.647 ns) 1.880 ns clock:inst\|Mux22~16 2 COMB LCCOMB_X24_Y13_N22 1 " "Info: 2: + IC(1.233 ns) + CELL(0.647 ns) = 1.880 ns; Loc. = LCCOMB_X24_Y13_N22; Fanout = 1; COMB Node = 'clock:inst\|Mux22~16'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.880 ns" { clock:inst|sec[5] clock:inst|Mux22~16 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 150 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.401 ns) + CELL(0.370 ns) 3.651 ns clock:inst\|Mux37~169 3 COMB LCCOMB_X26_Y12_N18 1 " "Info: 3: + IC(1.401 ns) + CELL(0.370 ns) = 3.651 ns; Loc. = LCCOMB_X26_Y12_N18; Fanout = 1; COMB Node = 'clock:inst\|Mux37~169'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.771 ns" { clock:inst|Mux22~16 clock:inst|Mux37~169 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 219 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.058 ns) + CELL(0.370 ns) 5.079 ns clock:inst\|Mux37~170 4 COMB LCCOMB_X25_Y13_N24 1 " "Info: 4: + IC(1.058 ns) + CELL(0.370 ns) = 5.079 ns; Loc. = LCCOMB_X25_Y13_N24; Fanout = 1; COMB Node = 'clock:inst\|Mux37~170'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.428 ns" { clock:inst|Mux37~169 clock:inst|Mux37~170 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 219 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.647 ns) 6.123 ns clock:inst\|Mux37~171 5 COMB LCCOMB_X25_Y13_N14 7 " "Info: 5: + IC(0.397 ns) + CELL(0.647 ns) = 6.123 ns; Loc. = LCCOMB_X25_Y13_N14; Fanout = 7; COMB Node = 'clock:inst\|Mux37~171'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.044 ns" { clock:inst|Mux37~170 clock:inst|Mux37~171 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 219 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.953 ns) + CELL(0.624 ns) 8.700 ns clock:inst\|Mux48~11 6 COMB LCCOMB_X27_Y8_N10 1 " "Info: 6: + IC(1.953 ns) + CELL(0.624 ns) = 8.700 ns; Loc. = LCCOMB_X27_Y8_N10; Fanout = 1; COMB Node = 'clock:inst\|Mux48~11'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.577 ns" { clock:inst|Mux37~171 clock:inst|Mux48~11 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 232 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.074 ns) + CELL(3.106 ns) 12.880 ns 78leddata\[3\] 7 PIN PIN_117 0 " "Info: 7: + IC(1.074 ns) + CELL(3.106 ns) = 12.880 ns; Loc. = PIN_117; Fanout = 0; PIN Node = '78leddata\[3\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.180 ns" { clock:inst|Mux48~11 78leddata[3] } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { -24 472 648 -8 "78leddata\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.764 ns ( 44.75 % ) " "Info: Total cell delay = 5.764 ns ( 44.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.116 ns ( 55.25 % ) " "Info: Total interconnect delay = 7.116 ns ( 55.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "12.880 ns" { clock:inst|sec[5] clock:inst|Mux22~16 clock:inst|Mux37~169 clock:inst|Mux37~170 clock:inst|Mux37~171 clock:inst|Mux48~11 78leddata[3] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "12.880 ns" { clock:inst|sec[5] {} clock:inst|Mux22~16 {} clock:inst|Mux37~169 {} clock:inst|Mux37~170 {} clock:inst|Mux37~171 {} clock:inst|Mux48~11 {} 78leddata[3] {} } { 0.000ns 1.233ns 1.401ns 1.058ns 0.397ns 1.953ns 1.074ns } { 0.000ns 0.647ns 0.370ns 0.370ns 0.647ns 0.624ns 3.106ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.088 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|sec[5] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.088 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|sec[5] {} } { 0.000ns 0.000ns 1.548ns 1.406ns 1.523ns 0.865ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "12.880 ns" { clock:inst|sec[5] clock:inst|Mux22~16 clock:inst|Mux37~169 clock:inst|Mux37~170 clock:inst|Mux37~171 clock:inst|Mux48~11 78leddata[3] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "12.880 ns" { clock:inst|sec[5] {} clock:inst|Mux22~16 {} clock:inst|Mux37~169 {} clock:inst|Mux37~170 {} clock:inst|Mux37~171 {} clock:inst|Mux48~11 {} 78leddata[3] {} } { 0.000ns 1.233ns 1.401ns 1.058ns 0.397ns 1.953ns 1.074ns } { 0.000ns 0.647ns 0.370ns 0.370ns 0.647ns 0.624ns 3.106ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}