prev_cmp_myshizhong.tan.qmsg

该程序实现一个数字钟

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { -24 -32 136 -8 "clk" "" } } } } { "e:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "key3 " "Info: Assuming node \"key3\" is an undefined clock" {  } { { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { 56 -32 136 72 "key3" "" } } } } { "e:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "key3" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clock:inst\|clk1khz " "Info: Detected ripple clock \"clock:inst\|clk1khz\" as buffer" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } } { "e:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock:inst\|clk1khz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clock:inst\|clk1hz " "Info: Detected ripple clock \"clock:inst\|clk1hz\" as buffer" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } } { "e:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock:inst\|clk1hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register clock:inst\|min\[2\] register clock:inst\|hour\[0\] 202.18 MHz 4.946 ns Internal " "Info: Clock \"clk\" has Internal fmax of 202.18 MHz between source register \"clock:inst\|min\[2\]\" and destination register \"clock:inst\|hour\[0\]\" (period= 4.946 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.683 ns + Longest register register " "Info: + Longest register to register delay is 4.683 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock:inst\|min\[2\] 1 REG LCFF_X25_Y12_N15 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y12_N15; Fanout = 12; REG Node = 'clock:inst\|min\[2\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock:inst|min[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.090 ns) + CELL(0.499 ns) 1.589 ns clock:inst\|Equal3~49 2 COMB LCCOMB_X24_Y12_N2 5 " "Info: 2: + IC(1.090 ns) + CELL(0.499 ns) = 1.589 ns; Loc. = LCCOMB_X24_Y12_N2; Fanout = 5; COMB Node = 'clock:inst\|Equal3~49'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { clock:inst|min[2] clock:inst|Equal3~49 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.381 ns) + CELL(0.206 ns) 2.176 ns clock:inst\|Equal3~50 3 COMB LCCOMB_X24_Y12_N4 1 " "Info: 3: + IC(0.381 ns) + CELL(0.206 ns) = 2.176 ns; Loc. = LCCOMB_X24_Y12_N4; Fanout = 1; COMB Node = 'clock:inst\|Equal3~50'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.587 ns" { clock:inst|Equal3~49 clock:inst|Equal3~50 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.386 ns) + CELL(0.370 ns) 2.932 ns clock:inst\|hour\[4\]~185 4 COMB LCCOMB_X24_Y12_N30 1 " "Info: 4: + IC(0.386 ns) + CELL(0.370 ns) = 2.932 ns; Loc. = LCCOMB_X24_Y12_N30; Fanout = 1; COMB Node = 'clock:inst\|hour\[4\]~185'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.756 ns" { clock:inst|Equal3~50 clock:inst|hour[4]~185 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.206 ns) 3.503 ns clock:inst\|hour\[4\]~186 5 COMB LCCOMB_X24_Y12_N6 5 " "Info: 5: + IC(0.365 ns) + CELL(0.206 ns) = 3.503 ns; Loc. = LCCOMB_X24_Y12_N6; Fanout = 5; COMB Node = 'clock:inst\|hour\[4\]~186'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { clock:inst|hour[4]~185 clock:inst|hour[4]~186 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.325 ns) + CELL(0.855 ns) 4.683 ns clock:inst\|hour\[0\] 6 REG LCFF_X24_Y12_N9 5 " "Info: 6: + IC(0.325 ns) + CELL(0.855 ns) = 4.683 ns; Loc. = LCFF_X24_Y12_N9; Fanout = 5; REG Node = 'clock:inst\|hour\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { clock:inst|hour[4]~186 clock:inst|hour[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.136 ns ( 45.61 % ) " "Info: Total cell delay = 2.136 ns ( 45.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.547 ns ( 54.39 % ) " "Info: Total interconnect delay = 2.547 ns ( 54.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.683 ns" { clock:inst|min[2] clock:inst|Equal3~49 clock:inst|Equal3~50 clock:inst|hour[4]~185 clock:inst|hour[4]~186 clock:inst|hour[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "4.683 ns" { clock:inst|min[2] {} clock:inst|Equal3~49 {} clock:inst|Equal3~50 {} clock:inst|hour[4]~185 {} clock:inst|hour[4]~186 {} clock:inst|hour[0] {} } { 0.000ns 1.090ns 0.381ns 0.386ns 0.365ns 0.325ns } { 0.000ns 0.499ns 0.206ns 0.370ns 0.206ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.088 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 9.088 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { -24 -32 136 -8 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.548 ns) + CELL(0.970 ns) 3.658 ns clock:inst\|clk1khz 2 REG LCFF_X18_Y10_N1 3 " "Info: 2: + IC(1.548 ns) + CELL(0.970 ns) = 3.658 ns; Loc. = LCFF_X18_Y10_N1; Fanout = 3; REG Node = 'clock:inst\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clk clock:inst|clk1khz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.406 ns) + CELL(0.970 ns) 6.034 ns clock:inst\|clk1hz 3 REG LCFF_X24_Y11_N9 2 " "Info: 3: + IC(1.406 ns) + CELL(0.970 ns) = 6.034 ns; Loc. = LCFF_X24_Y11_N9; Fanout = 2; REG Node = 'clock:inst\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.376 ns" { clock:inst|clk1khz clock:inst|clk1hz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.523 ns) + CELL(0.000 ns) 7.557 ns clock:inst\|clk1hz~clkctrl 4 COMB CLKCTRL_G4 18 " "Info: 4: + IC(1.523 ns) + CELL(0.000 ns) = 7.557 ns; Loc. = CLKCTRL_G4; Fanout = 18; COMB Node = 'clock:inst\|clk1hz~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.523 ns" { clock:inst|clk1hz clock:inst|clk1hz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.865 ns) + CELL(0.666 ns) 9.088 ns clock:inst\|hour\[0\] 5 REG LCFF_X24_Y12_N9 5 " "Info: 5: + IC(0.865 ns) + CELL(0.666 ns) = 9.088 ns; Loc. = LCFF_X24_Y12_N9; Fanout = 5; REG Node = 'clock:inst\|hour\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.531 ns" { clock:inst|clk1hz~clkctrl clock:inst|hour[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 41.22 % ) " "Info: Total cell delay = 3.746 ns ( 41.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.342 ns ( 58.78 % ) " "Info: Total interconnect delay = 5.342 ns ( 58.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.088 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|hour[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.088 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|hour[0] {} } { 0.000ns 0.000ns 1.548ns 1.406ns 1.523ns 0.865ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.087 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 9.087 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { -24 -32 136 -8 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.548 ns) + CELL(0.970 ns) 3.658 ns clock:inst\|clk1khz 2 REG LCFF_X18_Y10_N1 3 " "Info: 2: + IC(1.548 ns) + CELL(0.970 ns) = 3.658 ns; Loc. = LCFF_X18_Y10_N1; Fanout = 3; REG Node = 'clock:inst\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clk clock:inst|clk1khz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.406 ns) + CELL(0.970 ns) 6.034 ns clock:inst\|clk1hz 3 REG LCFF_X24_Y11_N9 2 " "Info: 3: + IC(1.406 ns) + CELL(0.970 ns) = 6.034 ns; Loc. = LCFF_X24_Y11_N9; Fanout = 2; REG Node = 'clock:inst\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.376 ns" { clock:inst|clk1khz clock:inst|clk1hz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.523 ns) + CELL(0.000 ns) 7.557 ns clock:inst\|clk1hz~clkctrl 4 COMB CLKCTRL_G4 18 " "Info: 4: + IC(1.523 ns) + CELL(0.000 ns) = 7.557 ns; Loc. = CLKCTRL_G4; Fanout = 18; COMB Node = 'clock:inst\|clk1hz~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.523 ns" { clock:inst|clk1hz clock:inst|clk1hz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.864 ns) + CELL(0.666 ns) 9.087 ns clock:inst\|min\[2\] 5 REG LCFF_X25_Y12_N15 12 " "Info: 5: + IC(0.864 ns) + CELL(0.666 ns) = 9.087 ns; Loc. = LCFF_X25_Y12_N15; Fanout = 12; REG Node = 'clock:inst\|min\[2\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.530 ns" { clock:inst|clk1hz~clkctrl clock:inst|min[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 41.22 % ) " "Info: Total cell delay = 3.746 ns ( 41.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.341 ns ( 58.78 % ) " "Info: Total interconnect delay = 5.341 ns ( 58.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.087 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|min[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.087 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|min[2] {} } { 0.000ns 0.000ns 1.548ns 1.406ns 1.523ns 0.864ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.088 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|hour[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.088 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|hour[0] {} } { 0.000ns 0.000ns 1.548ns 1.406ns 1.523ns 0.865ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.087 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|min[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.087 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|min[2] {} } { 0.000ns 0.000ns 1.548ns 1.406ns 1.523ns 0.864ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.683 ns" { clock:inst|min[2] clock:inst|Equal3~49 clock:inst|Equal3~50 clock:inst|hour[4]~185 clock:inst|hour[4]~186 clock:inst|hour[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "4.683 ns" { clock:inst|min[2] {} clock:inst|Equal3~49 {} clock:inst|Equal3~50 {} clock:inst|hour[4]~185 {} clock:inst|hour[4]~186 {} clock:inst|hour[0] {} } { 0.000ns 1.090ns 0.381ns 0.386ns 0.365ns 0.325ns } { 0.000ns 0.499ns 0.206ns 0.370ns 0.206ns 0.855ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.088 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|hour[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.088 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|hour[0] {} } { 0.000ns 0.000ns 1.548ns 1.406ns 1.523ns 0.865ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.087 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|min[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.087 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|min[2] {} } { 0.000ns 0.000ns 1.548ns 1.406ns 1.523ns 0.864ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}