myshizhong.map.qmsg

该程序实现一个数字钟

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 28 15:29:58 2008 " "Info: Processing started: Wed May 28 15:29:58 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off myshizhong -c myshizhong " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myshizhong -c myshizhong" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "myshizhong.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file myshizhong.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 myshizhong " "Info: Found entity 1: myshizhong" {  } { { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock-one " "Info: Found design unit 1: clock-one" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "myshizhong " "Info: Elaborating entity \"myshizhong\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "NOT inst1 " "Warning: Block or symbol \"NOT\" of instance \"inst1\" overlaps another block or symbol" {  } { { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { -8 168 216 24 "inst1" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "" 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "NOT inst3 " "Warning: Block or symbol \"NOT\" of instance \"inst3\" overlaps another block or symbol" {  } { { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { 48 168 216 80 "inst3" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock clock:inst " "Info: Elaborating entity \"clock\" for hierarchy \"clock:inst\"" {  } { { "myshizhong.bdf" "inst" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { -48 280 408 80 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "clock:inst\|\\process3:count\[0\] clock:inst\|cnt\[0\] " "Info: Duplicate register \"clock:inst\|\\process3:count\[0\]\" merged to single register \"clock:inst\|cnt\[0\]\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "clock:inst\|\\process2:count\[0\] clock:inst\|cnt\[0\] " "Info: Duplicate register \"clock:inst\|\\process2:count\[0\]\" merged to single register \"clock:inst\|cnt\[0\]\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "195 " "Info: Implemented 195 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "177 " "Info: Implemented 177 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "162 " "Info: Allocated 162 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 28 15:30:04 2008 " "Info: Processing ended: Wed May 28 15:30:04 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}