myshizhong.tan.qmsg

该程序实现一个数字钟

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "key3 register register clock:inst\|state\[0\] clock:inst\|state\[1\] 360.1 MHz Internal " "Info: Clock \"key3\" Internal fmax is restricted to 360.1 MHz between source register \"clock:inst\|state\[0\]\" and destination register \"clock:inst\|state\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.790 ns + Longest register register " "Info: + Longest register to register delay is 0.790 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock:inst\|state\[0\] 1 REG LCFF_X21_Y10_N11 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y10_N11; Fanout = 14; REG Node = 'clock:inst\|state\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock:inst|state[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.476 ns) + CELL(0.206 ns) 0.682 ns clock:inst\|state\[1\]~33 2 COMB LCCOMB_X21_Y10_N20 1 " "Info: 2: + IC(0.476 ns) + CELL(0.206 ns) = 0.682 ns; Loc. = LCCOMB_X21_Y10_N20; Fanout = 1; COMB Node = 'clock:inst\|state\[1\]~33'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.682 ns" { clock:inst|state[0] clock:inst|state[1]~33 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.790 ns clock:inst\|state\[1\] 3 REG LCFF_X21_Y10_N21 13 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.790 ns; Loc. = LCFF_X21_Y10_N21; Fanout = 13; REG Node = 'clock:inst\|state\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { clock:inst|state[1]~33 clock:inst|state[1] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 39.75 % ) " "Info: Total cell delay = 0.314 ns ( 39.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.476 ns ( 60.25 % ) " "Info: Total interconnect delay = 0.476 ns ( 60.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.790 ns" { clock:inst|state[0] clock:inst|state[1]~33 clock:inst|state[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "0.790 ns" { clock:inst|state[0] {} clock:inst|state[1]~33 {} clock:inst|state[1] {} } { 0.000ns 0.476ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key3 destination 3.940 ns + Shortest register " "Info: + Shortest clock path from clock \"key3\" to destination register is 3.940 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns key3 1 CLK PIN_99 2 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_99; Fanout = 2; CLK Node = 'key3'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { key3 } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { 56 -32 136 72 "key3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.290 ns) + CELL(0.666 ns) 3.940 ns clock:inst\|state\[1\] 2 REG LCFF_X21_Y10_N21 13 " "Info: 2: + IC(2.290 ns) + CELL(0.666 ns) = 3.940 ns; Loc. = LCFF_X21_Y10_N21; Fanout = 13; REG Node = 'clock:inst\|state\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.956 ns" { key3 clock:inst|state[1] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.650 ns ( 41.88 % ) " "Info: Total cell delay = 1.650 ns ( 41.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.290 ns ( 58.12 % ) " "Info: Total interconnect delay = 2.290 ns ( 58.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.940 ns" { key3 clock:inst|state[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "3.940 ns" { key3 {} key3~combout {} clock:inst|state[1] {} } { 0.000ns 0.000ns 2.290ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key3 source 3.940 ns - Longest register " "Info: - Longest clock path from clock \"key3\" to source register is 3.940 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns key3 1 CLK PIN_99 2 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_99; Fanout = 2; CLK Node = 'key3'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { key3 } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { 56 -32 136 72 "key3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.290 ns) + CELL(0.666 ns) 3.940 ns clock:inst\|state\[0\] 2 REG LCFF_X21_Y10_N11 14 " "Info: 2: + IC(2.290 ns) + CELL(0.666 ns) = 3.940 ns; Loc. = LCFF_X21_Y10_N11; Fanout = 14; REG Node = 'clock:inst\|state\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.956 ns" { key3 clock:inst|state[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.650 ns ( 41.88 % ) " "Info: Total cell delay = 1.650 ns ( 41.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.290 ns ( 58.12 % ) " "Info: Total interconnect delay = 2.290 ns ( 58.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.940 ns" { key3 clock:inst|state[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "3.940 ns" { key3 {} key3~combout {} clock:inst|state[0] {} } { 0.000ns 0.000ns 2.290ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.940 ns" { key3 clock:inst|state[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "3.940 ns" { key3 {} key3~combout {} clock:inst|state[1] {} } { 0.000ns 0.000ns 2.290ns } { 0.000ns 0.984ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.940 ns" { key3 clock:inst|state[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "3.940 ns" { key3 {} key3~combout {} clock:inst|state[0] {} } { 0.000ns 0.000ns 2.290ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.790 ns" { clock:inst|state[0] clock:inst|state[1]~33 clock:inst|state[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "0.790 ns" { clock:inst|state[0] {} clock:inst|state[1]~33 {} clock:inst|state[1] {} } { 0.000ns 0.476ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.940 ns" { key3 clock:inst|state[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "3.940 ns" { key3 {} key3~combout {} clock:inst|state[1] {} } { 0.000ns 0.000ns 2.290ns } { 0.000ns 0.984ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.940 ns" { key3 clock:inst|state[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "3.940 ns" { key3 {} key3~combout {} clock:inst|state[0] {} } { 0.000ns 0.000ns 2.290ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock:inst|state[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { clock:inst|state[1] {} } {  } {  } "" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 68 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "clock:inst\|min\[0\] key4 clk 2.883 ns register " "Info: tsu for register \"clock:inst\|min\[0\]\" (data pin = \"key4\", clock pin = \"clk\") is 2.883 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.789 ns + Longest pin register " "Info: + Longest pin to register delay is 11.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns key4 1 PIN PIN_97 2 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_97; Fanout = 2; PIN Node = 'key4'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { key4 } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { 80 -32 136 96 "key4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.817 ns) + CELL(0.370 ns) 8.181 ns clock:inst\|hour\[4\]~189 2 COMB LCCOMB_X21_Y10_N28 3 " "Info: 2: + IC(6.817 ns) + CELL(0.370 ns) = 8.181 ns; Loc. = LCCOMB_X21_Y10_N28; Fanout = 3; COMB Node = 'clock:inst\|hour\[4\]~189'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.187 ns" { key4 clock:inst|hour[4]~189 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.060 ns) + CELL(0.646 ns) 9.887 ns clock:inst\|min\[5\]~193 3 COMB LCCOMB_X21_Y10_N8 6 " "Info: 3: + IC(1.060 ns) + CELL(0.646 ns) = 9.887 ns; Loc. = LCCOMB_X21_Y10_N8; Fanout = 6; COMB Node = 'clock:inst\|min\[5\]~193'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.706 ns" { clock:inst|hour[4]~189 clock:inst|min[5]~193 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.047 ns) + CELL(0.855 ns) 11.789 ns clock:inst\|min\[0\] 4 REG LCFF_X21_Y11_N21 4 " "Info: 4: + IC(1.047 ns) + CELL(0.855 ns) = 11.789 ns; Loc. = LCFF_X21_Y11_N21; Fanout = 4; REG Node = 'clock:inst\|min\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.902 ns" { clock:inst|min[5]~193 clock:inst|min[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.865 ns ( 24.30 % ) " "Info: Total cell delay = 2.865 ns ( 24.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.924 ns ( 75.70 % ) " "Info: Total interconnect delay = 8.924 ns ( 75.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.789 ns" { key4 clock:inst|hour[4]~189 clock:inst|min[5]~193 clock:inst|min[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "11.789 ns" { key4 {} key4~combout {} clock:inst|hour[4]~189 {} clock:inst|min[5]~193 {} clock:inst|min[0] {} } { 0.000ns 0.000ns 6.817ns 1.060ns 1.047ns } { 0.000ns 0.994ns 0.370ns 0.646ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.866 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.866 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { -24 -32 136 -8 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.552 ns) + CELL(0.970 ns) 3.662 ns clock:inst\|clk1khz 2 REG LCFF_X20_Y4_N29 3 " "Info: 2: + IC(1.552 ns) + CELL(0.970 ns) = 3.662 ns; Loc. = LCFF_X20_Y4_N29; Fanout = 3; REG Node = 'clock:inst\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.522 ns" { clk clock:inst|clk1khz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.098 ns) + CELL(0.970 ns) 5.730 ns clock:inst\|clk1hz 3 REG LCFF_X24_Y4_N9 2 " "Info: 3: + IC(1.098 ns) + CELL(0.970 ns) = 5.730 ns; Loc. = LCFF_X24_Y4_N9; Fanout = 2; REG Node = 'clock:inst\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.068 ns" { clock:inst|clk1khz clock:inst|clk1hz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.612 ns) + CELL(0.000 ns) 7.342 ns clock:inst\|clk1hz~clkctrl 4 COMB CLKCTRL_G6 18 " "Info: 4: + IC(1.612 ns) + CELL(0.000 ns) = 7.342 ns; Loc. = CLKCTRL_G6; Fanout = 18; COMB Node = 'clock:inst\|clk1hz~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.612 ns" { clock:inst|clk1hz clock:inst|clk1hz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.858 ns) + CELL(0.666 ns) 8.866 ns clock:inst\|min\[0\] 5 REG LCFF_X21_Y11_N21 4 " "Info: 5: + IC(0.858 ns) + CELL(0.666 ns) = 8.866 ns; Loc. = LCFF_X21_Y11_N21; Fanout = 4; REG Node = 'clock:inst\|min\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.524 ns" { clock:inst|clk1hz~clkctrl clock:inst|min[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 42.25 % ) " "Info: Total cell delay = 3.746 ns ( 42.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.120 ns ( 57.75 % ) " "Info: Total interconnect delay = 5.120 ns ( 57.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.866 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|min[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.866 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|min[0] {} } { 0.000ns 0.000ns 1.552ns 1.098ns 1.612ns 0.858ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.789 ns" { key4 clock:inst|hour[4]~189 clock:inst|min[5]~193 clock:inst|min[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "11.789 ns" { key4 {} key4~combout {} clock:inst|hour[4]~189 {} clock:inst|min[5]~193 {} clock:inst|min[0] {} } { 0.000ns 0.000ns 6.817ns 1.060ns 1.047ns } { 0.000ns 0.994ns 0.370ns 0.646ns 0.855ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.866 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|min[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.866 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|min[0] {} } { 0.000ns 0.000ns 1.552ns 1.098ns 1.612ns 0.858ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk 78leddata\[2\] clock:inst\|min\[1\] 23.990 ns register " "Info: tco from clock \"clk\" to destination pin \"78leddata\[2\]\" through register \"clock:inst\|min\[1\]\" is 23.990 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.866 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.866 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { -24 -32 136 -8 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.552 ns) + CELL(0.970 ns) 3.662 ns clock:inst\|clk1khz 2 REG LCFF_X20_Y4_N29 3 " "Info: 2: + IC(1.552 ns) + CELL(0.970 ns) = 3.662 ns; Loc. = LCFF_X20_Y4_N29; Fanout = 3; REG Node = 'clock:inst\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.522 ns" { clk clock:inst|clk1khz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.098 ns) + CELL(0.970 ns) 5.730 ns clock:inst\|clk1hz 3 REG LCFF_X24_Y4_N9 2 " "Info: 3: + IC(1.098 ns) + CELL(0.970 ns) = 5.730 ns; Loc. = LCFF_X24_Y4_N9; Fanout = 2; REG Node = 'clock:inst\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.068 ns" { clock:inst|clk1khz clock:inst|clk1hz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.612 ns) + CELL(0.000 ns) 7.342 ns clock:inst\|clk1hz~clkctrl 4 COMB CLKCTRL_G6 18 " "Info: 4: + IC(1.612 ns) + CELL(0.000 ns) = 7.342 ns; Loc. = CLKCTRL_G6; Fanout = 18; COMB Node = 'clock:inst\|clk1hz~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.612 ns" { clock:inst|clk1hz clock:inst|clk1hz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.858 ns) + CELL(0.666 ns) 8.866 ns clock:inst\|min\[1\] 5 REG LCFF_X21_Y11_N23 11 " "Info: 5: + IC(0.858 ns) + CELL(0.666 ns) = 8.866 ns; Loc. = LCFF_X21_Y11_N23; Fanout = 11; REG Node = 'clock:inst\|min\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.524 ns" { clock:inst|clk1hz~clkctrl clock:inst|min[1] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 42.25 % ) " "Info: Total cell delay = 3.746 ns ( 42.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.120 ns ( 57.75 % ) " "Info: Total interconnect delay = 5.120 ns ( 57.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.866 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|min[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.866 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|min[1] {} } { 0.000ns 0.000ns 1.552ns 1.098ns 1.612ns 0.858ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.820 ns + Longest register pin " "Info: + Longest register to pin delay is 14.820 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock:inst\|min\[1\] 1 REG LCFF_X21_Y11_N23 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y11_N23; Fanout = 11; REG Node = 'clock:inst\|min\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock:inst|min[1] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(0.616 ns) 2.169 ns clock:inst\|Mux29~41 2 COMB LCCOMB_X20_Y10_N6 1 " "Info: 2: + IC(1.553 ns) + CELL(0.616 ns) = 2.169 ns; Loc. = LCCOMB_X20_Y10_N6; Fanout = 1; COMB Node = 'clock:inst\|Mux29~41'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.169 ns" { clock:inst|min[1] clock:inst|Mux29~41 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.392 ns) + CELL(0.651 ns) 3.212 ns clock:inst\|data~8 3 COMB LCCOMB_X20_Y10_N12 1 " "Info: 3: + IC(0.392 ns) + CELL(0.651 ns) = 3.212 ns; Loc. = LCCOMB_X20_Y10_N12; Fanout = 1; COMB Node = 'clock:inst\|data~8'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.043 ns" { clock:inst|Mux29~41 clock:inst|data~8 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.076 ns) + CELL(0.650 ns) 4.938 ns clock:inst\|Mux40~613 4 COMB LCCOMB_X22_Y10_N10 1 " "Info: 4: + IC(1.076 ns) + CELL(0.650 ns) = 4.938 ns; Loc. = LCCOMB_X22_Y10_N10; Fanout = 1; COMB Node = 'clock:inst\|Mux40~613'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.726 ns" { clock:inst|data~8 clock:inst|Mux40~613 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 219 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.392 ns) + CELL(0.651 ns) 5.981 ns clock:inst\|Mux40~614 5 COMB LCCOMB_X22_Y10_N28 1 " "Info: 5: + IC(0.392 ns) + CELL(0.651 ns) = 5.981 ns; Loc. = LCCOMB_X22_Y10_N28; Fanout = 1; COMB Node = 'clock:inst\|Mux40~614'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.043 ns" { clock:inst|Mux40~613 clock:inst|Mux40~614 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 219 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.918 ns) + CELL(0.651 ns) 8.550 ns clock:inst\|Mux40~617 6 COMB LCCOMB_X25_Y4_N14 7 " "Info: 6: + IC(1.918 ns) + CELL(0.651 ns) = 8.550 ns; Loc. = LCCOMB_X25_Y4_N14; Fanout = 7; COMB Node = 'clock:inst\|Mux40~617'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.569 ns" { clock:inst|Mux40~614 clock:inst|Mux40~617 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 219 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.510 ns) + CELL(0.615 ns) 10.675 ns clock:inst\|Mux52~34 7 COMB LCCOMB_X27_Y8_N12 1 " "Info: 7: + IC(1.510 ns) + CELL(0.615 ns) = 10.675 ns; Loc. = LCCOMB_X27_Y8_N12; Fanout = 1; COMB Node = 'clock:inst\|Mux52~34'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.125 ns" { clock:inst|Mux40~617 clock:inst|Mux52~34 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 232 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(3.106 ns) 14.820 ns 78leddata\[2\] 8 PIN PIN_116 0 " "Info: 8: + IC(1.039 ns) + CELL(3.106 ns) = 14.820 ns; Loc. = PIN_116; Fanout = 0; PIN Node = '78leddata\[2\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.145 ns" { clock:inst|Mux52~34 78leddata[2] } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { -24 472 648 -8 "78leddata\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.940 ns ( 46.83 % ) " "Info: Total cell delay = 6.940 ns ( 46.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.880 ns ( 53.17 % ) " "Info: Total interconnect delay = 7.880 ns ( 53.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "14.820 ns" { clock:inst|min[1] clock:inst|Mux29~41 clock:inst|data~8 clock:inst|Mux40~613 clock:inst|Mux40~614 clock:inst|Mux40~617 clock:inst|Mux52~34 78leddata[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "14.820 ns" { clock:inst|min[1] {} clock:inst|Mux29~41 {} clock:inst|data~8 {} clock:inst|Mux40~613 {} clock:inst|Mux40~614 {} clock:inst|Mux40~617 {} clock:inst|Mux52~34 {} 78leddata[2] {} } { 0.000ns 1.553ns 0.392ns 1.076ns 0.392ns 1.918ns 1.510ns 1.039ns } { 0.000ns 0.616ns 0.651ns 0.650ns 0.651ns 0.651ns 0.615ns 3.106ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.866 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|min[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.866 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|min[1] {} } { 0.000ns 0.000ns 1.552ns 1.098ns 1.612ns 0.858ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "14.820 ns" { clock:inst|min[1] clock:inst|Mux29~41 clock:inst|data~8 clock:inst|Mux40~613 clock:inst|Mux40~614 clock:inst|Mux40~617 clock:inst|Mux52~34 78leddata[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "14.820 ns" { clock:inst|min[1] {} clock:inst|Mux29~41 {} clock:inst|data~8 {} clock:inst|Mux40~613 {} clock:inst|Mux40~614 {} clock:inst|Mux40~617 {} clock:inst|Mux52~34 {} 78leddata[2] {} } { 0.000ns 1.553ns 0.392ns 1.076ns 0.392ns 1.918ns 1.510ns 1.039ns } { 0.000ns 0.616ns 0.651ns 0.650ns 0.651ns 0.651ns 0.615ns 3.106ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}