myshizhong.tan.qmsg

该程序实现一个数字钟

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { -24 -32 136 -8 "clk" "" } } } } { "e:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "key3 " "Info: Assuming node \"key3\" is an undefined clock" {  } { { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { 56 -32 136 72 "key3" "" } } } } { "e:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "key3" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clock:inst\|clk1khz " "Info: Detected ripple clock \"clock:inst\|clk1khz\" as buffer" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } } { "e:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock:inst\|clk1khz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clock:inst\|clk1hz " "Info: Detected ripple clock \"clock:inst\|clk1hz\" as buffer" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } } { "e:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock:inst\|clk1hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register clock:inst\|min\[3\] register clock:inst\|hour\[0\] 182.45 MHz 5.481 ns Internal " "Info: Clock \"clk\" has Internal fmax of 182.45 MHz between source register \"clock:inst\|min\[3\]\" and destination register \"clock:inst\|hour\[0\]\" (period= 5.481 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.223 ns + Longest register register " "Info: + Longest register to register delay is 5.223 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock:inst\|min\[3\] 1 REG LCFF_X20_Y10_N17 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y10_N17; Fanout = 17; REG Node = 'clock:inst\|min\[3\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock:inst|min[3] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.846 ns) + CELL(0.370 ns) 2.216 ns clock:inst\|Equal4~50 2 COMB LCCOMB_X21_Y10_N6 1 " "Info: 2: + IC(1.846 ns) + CELL(0.370 ns) = 2.216 ns; Loc. = LCCOMB_X21_Y10_N6; Fanout = 1; COMB Node = 'clock:inst\|Equal4~50'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.216 ns" { clock:inst|min[3] clock:inst|Equal4~50 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.381 ns) + CELL(0.206 ns) 2.803 ns clock:inst\|hour\[4\]~190 3 COMB LCCOMB_X21_Y10_N30 1 " "Info: 3: + IC(0.381 ns) + CELL(0.206 ns) = 2.803 ns; Loc. = LCCOMB_X21_Y10_N30; Fanout = 1; COMB Node = 'clock:inst\|hour\[4\]~190'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.587 ns" { clock:inst|Equal4~50 clock:inst|hour[4]~190 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.366 ns) + CELL(0.206 ns) 3.375 ns clock:inst\|hour\[4\]~191 4 COMB LCCOMB_X21_Y10_N0 5 " "Info: 4: + IC(0.366 ns) + CELL(0.206 ns) = 3.375 ns; Loc. = LCCOMB_X21_Y10_N0; Fanout = 5; COMB Node = 'clock:inst\|hour\[4\]~191'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.572 ns" { clock:inst|hour[4]~190 clock:inst|hour[4]~191 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.993 ns) + CELL(0.855 ns) 5.223 ns clock:inst\|hour\[0\] 5 REG LCFF_X22_Y11_N13 5 " "Info: 5: + IC(0.993 ns) + CELL(0.855 ns) = 5.223 ns; Loc. = LCFF_X22_Y11_N13; Fanout = 5; REG Node = 'clock:inst\|hour\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.848 ns" { clock:inst|hour[4]~191 clock:inst|hour[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.637 ns ( 31.34 % ) " "Info: Total cell delay = 1.637 ns ( 31.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.586 ns ( 68.66 % ) " "Info: Total interconnect delay = 3.586 ns ( 68.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.223 ns" { clock:inst|min[3] clock:inst|Equal4~50 clock:inst|hour[4]~190 clock:inst|hour[4]~191 clock:inst|hour[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "5.223 ns" { clock:inst|min[3] {} clock:inst|Equal4~50 {} clock:inst|hour[4]~190 {} clock:inst|hour[4]~191 {} clock:inst|hour[0] {} } { 0.000ns 1.846ns 0.381ns 0.366ns 0.993ns } { 0.000ns 0.370ns 0.206ns 0.206ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.006 ns - Smallest " "Info: - Smallest clock skew is 0.006 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.866 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.866 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { -24 -32 136 -8 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.552 ns) + CELL(0.970 ns) 3.662 ns clock:inst\|clk1khz 2 REG LCFF_X20_Y4_N29 3 " "Info: 2: + IC(1.552 ns) + CELL(0.970 ns) = 3.662 ns; Loc. = LCFF_X20_Y4_N29; Fanout = 3; REG Node = 'clock:inst\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.522 ns" { clk clock:inst|clk1khz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.098 ns) + CELL(0.970 ns) 5.730 ns clock:inst\|clk1hz 3 REG LCFF_X24_Y4_N9 2 " "Info: 3: + IC(1.098 ns) + CELL(0.970 ns) = 5.730 ns; Loc. = LCFF_X24_Y4_N9; Fanout = 2; REG Node = 'clock:inst\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.068 ns" { clock:inst|clk1khz clock:inst|clk1hz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.612 ns) + CELL(0.000 ns) 7.342 ns clock:inst\|clk1hz~clkctrl 4 COMB CLKCTRL_G6 18 " "Info: 4: + IC(1.612 ns) + CELL(0.000 ns) = 7.342 ns; Loc. = CLKCTRL_G6; Fanout = 18; COMB Node = 'clock:inst\|clk1hz~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.612 ns" { clock:inst|clk1hz clock:inst|clk1hz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.858 ns) + CELL(0.666 ns) 8.866 ns clock:inst\|hour\[0\] 5 REG LCFF_X22_Y11_N13 5 " "Info: 5: + IC(0.858 ns) + CELL(0.666 ns) = 8.866 ns; Loc. = LCFF_X22_Y11_N13; Fanout = 5; REG Node = 'clock:inst\|hour\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.524 ns" { clock:inst|clk1hz~clkctrl clock:inst|hour[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 42.25 % ) " "Info: Total cell delay = 3.746 ns ( 42.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.120 ns ( 57.75 % ) " "Info: Total interconnect delay = 5.120 ns ( 57.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.866 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|hour[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.866 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|hour[0] {} } { 0.000ns 0.000ns 1.552ns 1.098ns 1.612ns 0.858ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.860 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.860 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myshizhong.bdf" "" { Schematic "E:/Altera/myvhdl/myshizhong/myshizhong.bdf" { { -24 -32 136 -8 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.552 ns) + CELL(0.970 ns) 3.662 ns clock:inst\|clk1khz 2 REG LCFF_X20_Y4_N29 3 " "Info: 2: + IC(1.552 ns) + CELL(0.970 ns) = 3.662 ns; Loc. = LCFF_X20_Y4_N29; Fanout = 3; REG Node = 'clock:inst\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.522 ns" { clk clock:inst|clk1khz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.098 ns) + CELL(0.970 ns) 5.730 ns clock:inst\|clk1hz 3 REG LCFF_X24_Y4_N9 2 " "Info: 3: + IC(1.098 ns) + CELL(0.970 ns) = 5.730 ns; Loc. = LCFF_X24_Y4_N9; Fanout = 2; REG Node = 'clock:inst\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.068 ns" { clock:inst|clk1khz clock:inst|clk1hz } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.612 ns) + CELL(0.000 ns) 7.342 ns clock:inst\|clk1hz~clkctrl 4 COMB CLKCTRL_G6 18 " "Info: 4: + IC(1.612 ns) + CELL(0.000 ns) = 7.342 ns; Loc. = CLKCTRL_G6; Fanout = 18; COMB Node = 'clock:inst\|clk1hz~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.612 ns" { clock:inst|clk1hz clock:inst|clk1hz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.852 ns) + CELL(0.666 ns) 8.860 ns clock:inst\|min\[3\] 5 REG LCFF_X20_Y10_N17 17 " "Info: 5: + IC(0.852 ns) + CELL(0.666 ns) = 8.860 ns; Loc. = LCFF_X20_Y10_N17; Fanout = 17; REG Node = 'clock:inst\|min\[3\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.518 ns" { clock:inst|clk1hz~clkctrl clock:inst|min[3] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 42.28 % ) " "Info: Total cell delay = 3.746 ns ( 42.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.114 ns ( 57.72 % ) " "Info: Total interconnect delay = 5.114 ns ( 57.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.860 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|min[3] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.860 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|min[3] {} } { 0.000ns 0.000ns 1.552ns 1.098ns 1.612ns 0.852ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.866 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|hour[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.866 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|hour[0] {} } { 0.000ns 0.000ns 1.552ns 1.098ns 1.612ns 0.858ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.860 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|min[3] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.860 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|min[3] {} } { 0.000ns 0.000ns 1.552ns 1.098ns 1.612ns 0.852ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.223 ns" { clock:inst|min[3] clock:inst|Equal4~50 clock:inst|hour[4]~190 clock:inst|hour[4]~191 clock:inst|hour[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "5.223 ns" { clock:inst|min[3] {} clock:inst|Equal4~50 {} clock:inst|hour[4]~190 {} clock:inst|hour[4]~191 {} clock:inst|hour[0] {} } { 0.000ns 1.846ns 0.381ns 0.366ns 0.993ns } { 0.000ns 0.370ns 0.206ns 0.206ns 0.855ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.866 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|hour[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.866 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|hour[0] {} } { 0.000ns 0.000ns 1.552ns 1.098ns 1.612ns 0.858ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.860 ns" { clk clock:inst|clk1khz clock:inst|clk1hz clock:inst|clk1hz~clkctrl clock:inst|min[3] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.860 ns" { clk {} clk~combout {} clock:inst|clk1khz {} clock:inst|clk1hz {} clock:inst|clk1hz~clkctrl {} clock:inst|min[3] {} } { 0.000ns 0.000ns 1.552ns 1.098ns 1.612ns 0.852ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}