myshizhong.fit.qmsg

该程序实现一个数字钟

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.963 ns register register " "Info: Estimated most critical path is register to register delay of 5.963 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock:inst\|min\[1\] 1 REG LAB_X21_Y11 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X21_Y11; Fanout = 11; REG Node = 'clock:inst\|min\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock:inst|min[1] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.370 ns) 1.596 ns clock:inst\|Equal4~49 2 COMB LAB_X21_Y10 5 " "Info: 2: + IC(1.226 ns) + CELL(0.370 ns) = 1.596 ns; Loc. = LAB_X21_Y10; Fanout = 5; COMB Node = 'clock:inst\|Equal4~49'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.596 ns" { clock:inst|min[1] clock:inst|Equal4~49 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.370 ns) 2.407 ns clock:inst\|Equal4~50 3 COMB LAB_X21_Y10 1 " "Info: 3: + IC(0.441 ns) + CELL(0.370 ns) = 2.407 ns; Loc. = LAB_X21_Y10; Fanout = 1; COMB Node = 'clock:inst\|Equal4~50'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { clock:inst|Equal4~49 clock:inst|Equal4~50 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.370 ns) 3.218 ns clock:inst\|hour\[4\]~190 4 COMB LAB_X21_Y10 1 " "Info: 4: + IC(0.441 ns) + CELL(0.370 ns) = 3.218 ns; Loc. = LAB_X21_Y10; Fanout = 1; COMB Node = 'clock:inst\|hour\[4\]~190'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { clock:inst|Equal4~50 clock:inst|hour[4]~190 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.187 ns) + CELL(0.624 ns) 4.029 ns clock:inst\|hour\[4\]~191 5 COMB LAB_X21_Y10 5 " "Info: 5: + IC(0.187 ns) + CELL(0.624 ns) = 4.029 ns; Loc. = LAB_X21_Y10; Fanout = 5; COMB Node = 'clock:inst\|hour\[4\]~191'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { clock:inst|hour[4]~190 clock:inst|hour[4]~191 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.079 ns) + CELL(0.855 ns) 5.963 ns clock:inst\|hour\[0\] 6 REG LAB_X22_Y11 5 " "Info: 6: + IC(1.079 ns) + CELL(0.855 ns) = 5.963 ns; Loc. = LAB_X22_Y11; Fanout = 5; REG Node = 'clock:inst\|hour\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.934 ns" { clock:inst|hour[4]~191 clock:inst|hour[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/Altera/myvhdl/myshizhong/clock.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.589 ns ( 43.42 % ) " "Info: Total cell delay = 2.589 ns ( 43.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.374 ns ( 56.58 % ) " "Info: Total interconnect delay = 3.374 ns ( 56.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.963 ns" { clock:inst|min[1] clock:inst|Equal4~49 clock:inst|Equal4~50 clock:inst|hour[4]~190 clock:inst|hour[4]~191 clock:inst|hour[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X14_Y0 X28_Y14 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X14_Y0 to location X28_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITA