📄 clock.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port(clk:in std_logic;
clr:in std_logic;
en:in std_logic;
mode:in std_logic;
inc:in std_logic;
seg7:out std_logic_vector(6 downto 0);
scan:out std_logic_vector(5 downto 0)
);
end clock;
architecture one of clock is
signal state:std_logic_vector(1 downto 0);
signal qhh,qhl,qmh,qml,qsh,qsl:std_logic_vector(3 downto 0);
signal data:std_logic_vector(3 downto 0);
signal cnt:integer range 0 to 5;
signal clk1khz,clk1hz,clk2hz:std_logic;
signal blink:std_logic_vector(2 downto 0);
signal inc_reg:std_logic;
signal sec,min:integer range 0 to 59;
signal hour:integer range 0 to 23;
begin
process(clk)
variable count:integer range 0 to 24999;
begin
if clk'event and clk='1' then
if count=24999 then
clk1khz<=not clk1khz;
count:=0;
else
count:=count+1;
end if;
end if;
end process;
process(clk1khz)
variable count:integer range 0 to 499;
begin
if clk1khz'event and clk1khz='1'then
if count=499 then
clk1hz<=not clk1hz;
count:=0;
else
count:=count+1;
end if;
end if;
end process;
process(clk1khz)
variable count:integer range 0 to 249;
begin
if clk1khz'event and clk1khz='1'then
if count=249 then
clk2hz<=not clk2hz;
count:=0;
else
count:=count+1;
end if;
end if;
end process;
process(mode,clr)
begin
if clr='1'then
state<="00";
elsif mode'event and mode='0'then
state<=state+1;
end if;
end process;
process(clk1hz,state,en,clr,hour,sec,min)
begin
if en='1'then
hour<=hour;
min<=min;
sec<=sec;
elsif clr='1'then
hour<=0;
min<=0;
sec<=0;
elsif clk1hz'event and clk1hz='1'then
case state is
when"00"=>if sec=59 then sec<=0;
if min=59 then min<=0;
if hour=23 then hour<=0;
else hour<=hour+1;end if;
else min<=min+1;end if;
else sec<=sec+1;
end if;
when"01"=>if inc='1'then
if inc_reg='0'then inc_reg<='1';
if hour=23 then
hour<=0;
else hour<=hour+1;
end if;
end if;
else inc_reg<='0';
end if;
when"10"=>if inc='1'then
if inc_reg='0'then inc_reg<='1';
if min=59 then
min<=0;
else min<=min+1;
end if;
end if;
else inc_reg<='0';
end if;
when"11"=>if inc='1'then
if inc_reg='0'then inc_reg<='1';
if sec=59 then
sec<=0;
else sec<=sec+1;
end if;
end if;
else inc_reg<='0';
end if;
end case;
end if;
end process;
process(state,clk2hz)
begin
case state is
when"00"=>blink<="000";
when"01"=>blink<=(2=>clk2hz,others=>'0');
when"10"=>blink<=(1=>clk2hz,others=>'0');
when"11"=>blink<=(0=>clk2hz,others=>'0');
end case;
end process;
process(sec)
begin
case sec is
when 0|10|20|30|40|50=>qsl<="0000";
when 1|11|21|31|41|51=>qsl<="0001";
when 2|12|22|32|42|52=>qsl<="0010";
when 3|13|23|33|43|53=>qsl<="0011";
when 4|14|24|34|44|54=>qsl<="0100";
when 5|15|25|35|45|55=>qsl<="0101";
when 6|16|26|36|46|56=>qsl<="0110";
when 7|17|27|37|47|57=>qsl<="0111";
when 8|18|28|38|48|58=>qsl<="1000";
when 9|19|29|39|49|59=>qsl<="1001";
when others=>null;
end case;
case sec is
when 0|1|2|3|4|5|6|7|8|9=>qsh<="0000";
when 10|11|12|13|14|15|16|17|18|19=>qsh<="0001";
when 20|21|22|23|24|25|26|27|28|29=>qsh<="0010";
when 30|31|32|33|34|35|36|37|38|39=>qsh<="0011";
when 40|41|42|43|44|45|46|47|48|49=>qsh<="0100";
when 50|51|52|53|54|55|56|57|58|59=>qsh<="0101";
end case;
end process;
process(min)
begin
case min is
when 0|10|20|30|40|50=>qml<="0000";
when 1|11|21|31|41|51=>qml<="0001";
when 2|12|22|32|42|52=>qml<="0010";
when 3|13|23|33|43|53=>qml<="0011";
when 4|14|24|34|44|54=>qml<="0100";
when 5|15|25|35|45|55=>qml<="0101";
when 6|16|26|36|46|56=>qml<="0110";
when 7|17|27|37|47|57=>qml<="0111";
when 8|18|28|38|48|58=>qml<="1000";
when 9|19|29|39|49|59=>qml<="1001";
when others=>null;
end case;
case min is
when 0|1|2|3|4|5|6|7|8|9=>qmh<="0000";
when 10|11|12|13|14|15|16|17|18|19=>qmh<="0001";
when 20|21|22|23|24|25|26|27|28|29=>qmh<="0010";
when 30|31|32|33|34|35|36|37|38|39=>qmh<="0011";
when 40|41|42|43|44|45|46|47|48|49=>qmh<="0100";
when 50|51|52|53|54|55|56|57|58|59=>qmh<="0101";
end case;
end process;
process(hour)
begin
case hour is
when 0|10|20=>qhl<="0000";
when 1|11|21=>qhl<="0001";
when 2|12|22=>qhl<="0010";
when 3|13|23=>qhl<="0011";
when 4|14=>qhl<="0100";
when 5|15=>qhl<="0101";
when 6|16=>qhl<="0110";
when 7|17=>qhl<="0111";
when 8|18=>qhl<="1000";
when 9|19=>qhl<="1001";
when others=>null;
end case;
case hour is
when 0|1|2|3|4|5|6|7|8|9=>qhh<="0000";
when 10|11|12|13|14|15|16|17|18|19=>qhh<="0001";
when 20|21|22|23=>qhh<="0010";
when others=>null;
end case;
end process;
process (clk1khz)
begin
if clk1khz'event and clk1khz='1' then
if cnt=5 then cnt<=0;
else cnt<=cnt+1;
end if;
end if;
end process;
process(cnt,qhh,qhl,qmh,qml,qsh,qsl,blink)
begin
case cnt is
when 0=>data<=qsl or (blink(0)&blink(0)&blink(0)&blink(0));scan<="111110";
when 1=>data<=qsh or (blink(0)&blink(0)&blink(0)&blink(0));scan<="111101";
when 2=>data<=qml or (blink(1)&blink(1)&blink(1)&blink(1));scan<="111011";
when 3=>data<=qmh or (blink(1)&blink(1)&blink(1)&blink(1));scan<="110111";
when 4=>data<=qhl or (blink(2)&blink(2)&blink(2)&blink(2));scan<="101111";
when 5=>data<=qhh or (blink(2)&blink(2)&blink(2)&blink(2));scan<="011111";
when others=>null;
end case;
end process;
process(data)
begin
case data is
WHEN"0000"=>seg7<="1000000";
WHEN"0001"=>seg7<="1111001";
WHEN"0010"=>seg7<="0100100";
WHEN"0011"=>seg7<="0110000";
WHEN"0100"=>seg7<="0011001";
WHEN"0101"=>seg7<="0010010";
WHEN"0110"=>seg7<="0000010";
WHEN"0111"=>seg7<="1111000";
WHEN"1000"=>seg7<="0000000";
WHEN"1001"=>seg7<="0010000";
WHEN others=>seg7<="0000000";
end case;
end process;
end one;
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