myshizhong.map.rpt

该程序实现一个数字钟

; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                               ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path               ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------+
; myshizhong.bdf                   ; yes             ; User Block Diagram/Schematic File  ; E:/Altera/myvhdl/myshizhong/myshizhong.bdf ;
; clock.vhd                        ; yes             ; User VHDL File                     ; E:/Altera/myvhdl/myshizhong/clock.vhd      ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------+


+------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                      ;
+---------------------------------------------+--------------------+
; Resource                                    ; Usage              ;
+---------------------------------------------+--------------------+
; Estimated Total logic elements              ; 177                ;
;                                             ;                    ;
; Total combinational functions               ; 177                ;
; Logic element usage by number of LUT inputs ;                    ;
;     -- 4 input functions                    ; 97                 ;
;     -- 3 input functions                    ; 24                 ;
;     -- <=2 input functions                  ; 56                 ;
;                                             ;                    ;
; Logic elements by mode                      ;                    ;
;     -- normal mode                          ; 136                ;
;     -- arithmetic mode                      ; 41                 ;
;                                             ;                    ;
; Total registers                             ; 56                 ;
;     -- Dedicated logic registers            ; 56                 ;
;     -- I/O registers                        ; 0                  ;
;                                             ;                    ;
; I/O pins                                    ; 18                 ;
; Maximum fan-out node                        ; clock:inst|clk1khz ;
; Maximum fan-out                             ; 21                 ;
; Total fan-out                               ; 725                ;
; Average fan-out                             ; 2.89               ;
+---------------------------------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                            ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name    ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------+--------------+
; |myshizhong                ; 177 (0)           ; 56 (0)       ; 0           ; 0            ; 0       ; 0         ; 18   ; 0            ; |myshizhong            ; work         ;
;    |clock:inst|            ; 177 (177)         ; 56 (56)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |myshizhong|clock:inst ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------+
; Registers Removed During Synthesis                                    ;
+---------------------------------------+-------------------------------+
; Register name                         ; Reason for Removal            ;
+---------------------------------------+-------------------------------+
; clock:inst|\process3:count[0]         ; Merged with clock:inst|cnt[0] ;
; clock:inst|\process2:count[0]         ; Merged with clock:inst|cnt[0] ;
; Total Number of Removed Registers = 2 ;                               ;
+---------------------------------------+-------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 56    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 19    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 17    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; 6:1                ; 6 bits    ; 24 LEs        ; 6 LEs                ; 18 LEs                 ; Yes        ; |myshizhong|clock:inst|sec[3]  ;
; 7:1                ; 6 bits    ; 24 LEs        ; 6 LEs                ; 18 LEs                 ; Yes        ; |myshizhong|clock:inst|min[5]  ;
; 8:1                ; 5 bits    ; 25 LEs        ; 5 LEs                ; 20 LEs                 ; Yes        ; |myshizhong|clock:inst|hour[1] ;
; 6:1                ; 4 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |myshizhong|clock:inst|Mux41   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Wed May 28 15:29:58 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myshizhong -c myshizhong
Info: Found 1 design units, including 1 entities, in source file myshizhong.bdf
    Info: Found entity 1: myshizhong
Info: Found 2 design units, including 1 entities, in source file clock.vhd
    Info: Found design unit 1: clock-one
    Info: Found entity 1: clock
Info: Elaborating entity "myshizhong" for the top level hierarchy
Warning: Block or symbol "NOT" of instance "inst1" overlaps another block or symbol
Warning: Block or symbol "NOT" of instance "inst3" overlaps another block or symbol
Info: Elaborating entity "clock" for hierarchy "clock:inst"
Info: Duplicate registers merged to single register
    Info: Duplicate register "clock:inst|\process3:count[0]" merged to single register "clock:inst|cnt[0]"
    Info: Duplicate register "clock:inst|\process2:count[0]" merged to single register "clock:inst|cnt[0]"
Info: Implemented 195 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 13 output pins
    Info: Implemented 177 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Allocated 162 megabytes of memory during processing
    Info: Processing ended: Wed May 28 15:30:04 2008
    Info: Elapsed time: 00:00:06