syn_tran_tb.v

同步传输的vhdl实现

//-----------------------------------------------------------------------------
//
// Title       : syn_tran_tb
// Design      : syn_tran
// Author      : yhy
// Company     : asic
//
//-----------------------------------------------------------------------------
//
// File        : syn_tran_TB.v
// Generated   : Wed May 23 15:20:58 2007
// From        : d:\yhy\syn_tran\syn_tran\src\TestBench\syn_tran_TB_settings.txt
// By          : tb_verilog.pl ver. ver 1.2s
//
//-----------------------------------------------------------------------------
//
// Description : 
//
//-----------------------------------------------------------------------------
module syn_tran_tb;


//Internal signals declarations:
reg ale;
reg clk;
reg cs;
wire [7:0]d_bidir;
reg [7:0]d;
//Continous assignment for inout port "d".
assign d_bidir =(ale==1'b1 || wr==1'b0)? d:8'hzz;

reg fs;
reg rd;
reg rst_n;
wire txd;
reg  wr;



// Unit Under Test port map
	syn_tran UUT (
		.ale(ale),
		.clk(clk),
		.cs(cs),
		.d(d_bidir),
		.fs(fs),
		.rd(rd),
		.rst_n(rst_n),
		.txd(txd),
		.wr(wr));

initial	
	begin
		cs=1;
		wr=1;
		rd=1;  
		fs=1;
		ale=0;	
		d=8'h01;
		rst_n=0;
		clk=0;
		#40 rst_n=1; 
	end
	
always #5 clk=!clk;
	

initial 
	begin
		#45 ale=1;
		    d=8'h00;
		#10 ale=0; 
		    cs=0;
		#10 d=8'h0f;
		    wr=0; 
		#10 cs=0;
		     wr=0; //one cir
		#10 ale=1;
		    cs=1;
		    wr=1;
		    d=8'h00;
		#10 ale=0; 
		    cs=0;
		#10 d=8'hC0;
		    wr=0; 
		#10 cs=0;
		    wr=0; //one cir	
		#10 ale=1; 
		    cs=1;
		    wr=1;
		    d=8'h01;
		#10 ale=0; 
		    cs=0;
		#10 d=8'h0E;
		    wr=0; 
		#10 cs=0;
		     wr=0; //one cir
		#10 ale=1;
		    cs=1;
		    wr=1;
		    d=8'h01;
		#10 ale=0; 
		    cs=0;
		#10 d=8'h33;
		    wr=0; 
		#10 cs=0;
		    wr=0; //one cir
		#10 ale=1;
		    cs=1;
		    wr=1;
		    d=8'h00;
		#10 ale=0; 
		    cs=0;
		#10 d=8'h0F;
		    wr=0; 
		#10 cs=0;
		    wr=0; //one cir
		#10 ale=1;
		    cs=1;
		    wr=1;
		    d=8'h00;
		#10 ale=0; 
		    cs=0;
		#10 d=8'hC0;
		    wr=0; 
		#10 cs=0;
            wr=0; //one cir	 
		#10 ale=1;
		    cs=1;
		    wr=1;
		    d=8'h01;
		#10 ale=0; 
		    cs=0;
		#10 d=8'h04;
		    wr=0; 
		#10 cs=0;
		wr=0; //one cir
	    #10 ale=1;
		    cs=1;
		    wr=1;
		    rd=1;
		    d=8'h00;
		#10 ale=0; 
		    cs=0;
		#10 rd=0; 
		#10 cs=0;
		rd=0; //one cir	
		#10 ale=1;
		    cs=1;
		    rd=1;
		    d=8'h00;
		#10 ale=0; 
		    cs=0;
		#10 rd=0; 
		#10 cs=0;
		rd=0; //one cir	
		#10 rd=1;
	end
		
initial
	begin
		#150 fs=0;
		#10  fs=1;
		#2900 fs=0; 
		#10  fs=1;
	end
		

endmodule