syn_tran.plg

来自「同步传输的vhdl实现」· PLG 代码 · 共 12 行

@P:  Worst Slack : 994.743
@P:  syn_tran|clk - Estimated Frequency : 190.2 MHz
@P:  syn_tran|clk - Requested Frequency : 1.0 MHz
@P:  syn_tran|clk - Estimated Period : 5.257
@P:  syn_tran|clk - Requested Period : 1000.000
@P:  syn_tran|clk - Slack : 994.743
@P: syn_tran Part : xc2v40cs144-6
@P: syn_tran I/O primitives : 15
@P: syn_tran I/O Register bits : 0
@P: syn_tran Register bits (Non I/O) : 104 (20%)
@P: syn_tran Total Luts : 149 (29%)