syn_tran_tb_runtest.do
来自「同步传输的vhdl实现」· DO 代码 · 共 22 行
DO
22 行
SetActiveLib -work
#Compiling UUT module design files
comp -include $DSN\src\syn_tran.v
comp -include "$DSN\src\TestBench\syn_tran_TB.v"
asim syn_tran_tb
wave
wave -noreg ale
wave -noreg clk
wave -noreg cs
wave -noreg d
wave -noreg d_bidir
wave -noreg fs
wave -noreg rd
wave -noreg rst_n
wave -noreg txd
wave -noreg wr
run
#End simulation macro
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