syn_tran_tb_runtest.do

同步传输的vhdl实现

SetActiveLib -work
#Compiling UUT module design files
comp -include $DSN\src\syn_tran.v
comp -include "$DSN\src\TestBench\syn_tran_TB.v"
asim syn_tran_tb

wave
wave -noreg ale
wave -noreg clk
wave -noreg cs
wave -noreg d
wave -noreg d_bidir
wave -noreg fs
wave -noreg rd
wave -noreg rst_n
wave -noreg txd
wave -noreg wr

run

#End simulation macro