syn_tran_tb_settings.txt

同步传输的vhdl实现

[SETTINGS]
UUT_module%syn_tran%
TB_module%syn_tran_tb%
DSN_PATH%$DSN\src\TestBench%
OUTPUT_DIRECTORY%d:\yhy\syn_tran\syn_tran\src\TestBench%
STIMULUS%NO%
VECTORS_FILE%%
AWF_FILE%%
TB_FILE%syn_tran_TB.v%
MACRO_FILE%syn_tran_TB_runtest.do%
UUT_module_FILE%syn_tran/src/syn_tran.v%
LIBRARY_NAME%syn_tran%
LIBRARY_TYPE%work%
TestBench_TYPE%simple%
ENABLE_FILE%none%
RESULT_FILE%none%

[GENERICS]

[PORTS]
ale%in%wire%NO%NOCLK%
clk%in%wire%NO%NOCLK%
cs%in%wire%NO%NOCLK%
d%inout%[7:0]wire%NO%NOCLK%
fs%in%wire%NO%NOCLK%
rd%in%wire%NO%NOCLK%
rst_n%in%wire%NO%NOCLK%
txd%out%wire%NO%NOCLK%
wr%in%wire%NO%NOCLK%

[SDF]

[INCLUDE]
[Verilog_FILES]
$DSN\src\syn_tran.v