test1.msg

同步传输的vhdl实现

@TM:1179922616
@N: FX164 :"":0:0:0:-1|The option to pack flops in the IOB has not been specified 
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N:  :"d:\yhy\syn_tran\syn_tran\syn_tran.v":51:8:51:10|Synthesizing module TSR
@W:  :"d:\yhy\syn_tran\syn_tran\syn_tran.v":60:15:60:22|M
@N:  :"d:\yhy\syn_tran\syn_tran\syn_tran.v":288:8:288:10|Synthesizing module THR
@N:  :"d:\yhy\syn_tran\syn_tran\syn_tran.v":450:7:450:14|Synthesizing module syn_tran