frequency_div256.vhd

dds频率生成文件

library ieee;
use ieee.std_logic_1164.all;

ENTITY frequency_div256 IS
	PORT
	(
		frein : IN	STD_LOGIC;
		freout: OUT	STD_LOGIC
	);
END frequency_div256;
ARCHITECTURE behave OF frequency_div256 IS
	SIGNAL count: integer range 0 to 127;
	SIGNAL clk : STD_LOGIC;
BEGIN
	process(frein)
	begin
	if frein'event and frein='1' then
		if count=127 then
			count<=0;
			clk<=not clk;
		else count<=count+1;
		end if;
	end if;
	end process;
	freout<=clk;
END behave;