dds_cordic.qsf

dds频率生成文件

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		CORDIC_DDS_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY DDS_CORDIC
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:59:05  AUGUST 12, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
set_global_assignment -name VHDL_FILE lpm_add_sub_16bit.vhd
set_global_assignment -name VHDL_FILE cordic_m1_rot.vhd
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name VECTOR_WAVEFORM_FILE ../cordic_m1_rot/cordic_m1_rot.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE CORDIC_DDS.vwf
set_location_assignment PIN_209 -to sys_clk
set_location_assignment PIN_118 -to daclk
set_location_assignment PIN_117 -to OUT[15]
set_location_assignment PIN_116 -to OUT[14]
set_location_assignment PIN_114 -to OUT[13]
set_location_assignment PIN_113 -to OUT[12]
set_location_assignment PIN_111 -to OUT[11]
set_location_assignment PIN_110 -to OUT[10]
set_location_assignment PIN_109 -to OUT[9]
set_location_assignment PIN_106 -to OUT[8]
set_location_assignment PIN_105 -to OUT[7]
set_location_assignment PIN_100 -to OUT[6]
set_location_assignment PIN_97 -to OUT[5]
set_location_assignment PIN_96 -to OUT[4]
set_location_assignment PIN_90 -to OUT[3]
set_location_assignment PIN_88 -to OUT[2]
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE CORDIC_DDS.stp
set_global_assignment -name VHDL_FILE frequency_div256.vhd
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name BDF_FILE DDS_CORDIC.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE DDS_CORDIC.vwf
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation