seg7_display.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  seg7_display.vhd -- 
------------------------------------------------------------------------
--  Authors : Albert Zemba & Mihai Cucicea
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1i 
--                   WebPack
------------------------------------------------------------------------
-- This source file contains the seg7_display component
------------------------------------------------------------------------
--  Behavioral description
-- on the inputs it receives what it should display on the 7 segment 
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity seg7_display is
	port( d1,d2,d3,d4:in std_logic_vector (3 downto 0);
			clk:in std_logic;
			an1,an2,an3,an4:out std_logic;
			ca,cb,cc,cd,ce,cf,cg:out std_logic
		 );
end seg7_display;

architecture Behavioral of seg7_display is

component rom_digits is
	port( add: in std_logic_vector(3 downto 0); 
			digit : out std_logic_vector(6 downto 0)
	);
end component rom_digits;

component num_2bits is
	port( clk:in std_logic;
			val:out std_logic_vector (1 downto 0)
		 );
end component num_2bits;

component decod_2bits is
	port( i:in std_logic_vector (1 downto 0);
			o0,o1,o2,o3:out std_logic
		 );
end component decod_2bits;

component mux4_1_4bits is
	port( i0,i1,i2,i3:in std_logic_vector (3 downto 0);
			s:in std_logic_vector (1 downto 0);
			o:out std_logic_vector (3 downto 0)
		 );
end component mux4_1_4bits;

component div_clk_381hz is
	port(clock_50Mhz:in std_logic;
			clk17b:out std_logic);
end component div_clk_381hz;

signal num_out:std_logic_vector (1 downto 0);
signal mux_out:std_logic_vector (3 downto 0);
signal dig:std_logic_vector (6 downto 0);
signal clk17b:std_logic;

begin

	ca<=dig(6);
	cb<=dig(5);
	cc<=dig(4);
	cd<=dig(3);
	ce<=dig(2);
	cf<=dig(1);
	cg<=dig(0);

	divclk : div_clk_381hz port map (clock_50Mhz=>clk,clk17b=>clk17b);
	num : num_2bits port map (clk=>clk17b,val=>num_out);
	decod : decod_2bits 
		port map (i=>num_out,o0=>an1,o1=>an2,o2=>an3,o3=>an4);
	mux : mux4_1_4bits 
		port map (i0=>d1,i1=>d2,i2=>d3,i3=>d4,s=>num_out,o=>mux_out);
	rom : rom_digits port map (add=>mux_out,digit=>dig);

end Behavioral;