reg_6bits.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 44 行

------------------------------------------------------------------------
--  reg_6bits.vhd -- 
------------------------------------------------------------------------
--  Authors : Albert Zemba & Mihai Cucicea
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1i 
--                   WebPack
------------------------------------------------------------------------
-- This source file contains the reg_6bits component
------------------------------------------------------------------------
--  Behavioral description
-- A 6 bit register with reset and load
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity reg_6bits is
port(clk, reset, load: in std_logic; 
		a : in std_logic_vector(5 downto 0);
		y : out std_logic_vector(5 downto 0):= "000001"
	);
end reg_6bits;

architecture Behavioral of reg_6bits is

begin
	process (clk)
	begin
		if (clk'event and clk = '1') then
			if (reset='1') then
				y<="000001";
			else
				if (load='1') then
					y <= a;	
				end if;
			end if;
		end if;
	end process;

end Behavioral;