div_clk_6hz.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 39 行

------------------------------------------------------------------------
--  div_clk_6hz.vhd -- 
------------------------------------------------------------------------
--  Authors : Albert Zemba & Mihai Cucicea
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1i 
--                   WebPack
------------------------------------------------------------------------
-- This source file contains the div_clk_6hz component
------------------------------------------------------------------------
--  Behavioral description
-- Divides the input clock(50Mhz) to 6hz
-- The output is required for the light input clock 
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity div_clk_6hz is
	port(clock_50Mhz:in std_logic;
			clk23b:out std_logic);
end div_clk_6hz;

architecture Behavioral of div_clk_6hz is
signal clk : std_logic_vector(22 downto 0)
	:= "00000000000000000000000";
begin

	 process (clock_50Mhz)
	 	begin
			if clock_50Mhz = '1' and clock_50Mhz'event then 
				clk <= clk + 1;
			end if;
		clk23b <= clk(22);
	 end process;

end Behavioral;