div16.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 35 行

------------------------------------------------------------------------
--  div16.vhd -- 
------------------------------------------------------------------------
--  Authors : Albert Zemba & Mihai Cucicea
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1i 
--                   WebPack
------------------------------------------------------------------------
-- This source file contains the div16 component
------------------------------------------------------------------------
--  Behavioral description
-- returns the inputs modulo 16
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity div16 is
	port(pixel_row,pixel_col:in std_logic_vector(9 downto 0);
			p_r,p_c:out std_logic_vector (5 downto 0)
	);
end div16;

architecture Behavioral of div16 is

begin

		process (pixel_row,pixel_col)
		begin
			p_r <= conv_std_logic_vector(conv_integer(pixel_row)/16,7);
			p_c <= conv_std_logic_vector(conv_integer(pixel_col)/16,7);
		end process;

end Behavioral;